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Intentional electromagnetic interference is a serious threat to the safety of electronic devices. Multiple electromagnetic pulses will be coupled and transmitted to electronic devices through the cables. Accumulative effects are generated, which make it easier for damage to occur in the electronic devices. In this article, the working principle of micro-silicon acceleration sensors is introduced. The accumulative effects of multiple pulses on acceleration sensors is studied by a large number of injection experiments. The accumulation trends of multiple pulses with different pulse numbers and intervals are analyzed. The damaged structures inside abnormal sensor amplifiers were observed via optical microscopy and scanning electron microscopy. The experimental results show that the accumulative effect is strengthened with increased pulse number or decreased pulse interval, and the threshold voltage for multiple pulses on the acceleration sensor decreases. The threshold voltage for a single pulse is 321.57 V. When the pulse interval is 1 μs and the pulse number is 5, the threshold voltage for multiple pulses is 163.42 V, which is reduced by 49.12% compared with a single pulse. These results provide a reference for the damage design of electromagnetic pulse weapons.

This work presents a 300-GHz low-noise amplifier (LNA) in a SiGe:C 130-nm BiCMOS technology, featuring $f_{t}$/$f_{max}$ of 470/700 GHz. The designed amplifier uses three cascaded stages in a pseudo-differential cascode topology with input and output baluns facilitating single-ended measurements. The first stage is matched trading off noise and gain performance, while a T-type output matching network is used for broadband matching. The interstage matching is performed using center tap transformers. On-wafer measurements show that the designed LNA has a peak small-signal gain of 10.8 dB at 325 GHz, along with a 3-dB bandwidth of 68 GHz and an input 1-dB compression point of -15.6 dBm at 287.5 GHz. The simulated noise figure is better than 12.7 dB over the required band. The circuit occupies 0.26-mm² silicon area and consumes 119 mW from a 3.3-V supply.

Development of transistors for advanced low noise amplifiers requires better understanding of mechanisms governing the charge carrier transport in correlation with the noise performance. In this paper, we report on study of the carrier velocity in InGaAs/InP high-electron-mobility transistors (HEMTs) found via geometrical magnetoresistance in the wide range of the drain fields, up to 2 kV/cm, at cryogenic temperature of 2 K. We observed, for the first time experimentally, the velocity peaks with peak velocity and corresponding field decreasing significantly with the transverse field. The low-field mobility and peak velocity are found to be up to 65000 cm2/Vs and 1.2x106 cm/s, respectively. Extrapolations to the lower transverse fields show that the peak velocity can be as high as 2.7x107 cm/s. The corresponding intrinsic transit frequency can be up to 172 GHz at the gate length of 250 nm. We demonstrated, for the first time, that the low-field mobility and peak velocity reveal opposite dependencies on the transverse field, indicating the difference in carrier transport mechanisms dominating at low- and high-fields. Therefore, the peak velocity is an appropriate parameter for characterization and development of the low noise HEMTs, complementary to the low-field mobility. The results of the research clarify the ways of the further development of the HEMTs for advanced applications.

This letter presents an ultra-compact two-stage 60-GHz differential bi-directional amplifier (DBA) design in a 65-nm CMOS process. To satisfy the stability and gain requirements, a differential neutralized bi-directional common-source gain cell combined with the cross-coupled gm-boosting technique is proposed. In addition, a layout-symmetrical coupled line transformer is used as the inter-stage matching network to achieve broadband operation, reducing insertion loss and ensuring identical responses in both forward/backward modes. The proposed DBA achieves a peak gain of 16.1 dB with a 3-dB bandwidth of 15 GHz (52-67 GHz), maximum OP $_{{1 ,,dB}}$ of 5.1 dBm, $P_{{SAT}}$ of 9.6 dBm, a peak PAE of 11.5% at 62 GHz, respectively, consuming 70 mW from a power supply of 1.2 V. The circuit core occupies an ultra-compact area of only 0.0675 mm².

Low-noise optical amplification has been a long-lasting research topic in various fields including communication, metrology and quantum optics. Here we report optical signal processing at different wavelengths enabled by a low-noise optical phase-sensitive amplifier (PSA) using a single compact integrated silicon nitride photonic waveguide. For 10 Gbit/s non-return-to-zero optical signals with central wavelengths tuned in the telecommunication band, the waveguide-based PSA exhibits a gain of more than 10 dB and a noise figure of about 1.2 dB when the coupling losses are neglected. For a bit-error-rate level of 10-9, penalties of less than 0.8 dB for all channels are observed after the signals propagation through the chip-based PSA, which may be due to the distortions in the few-mode waveguide. These experimental results generally agree with theoretical prediction and indicate that silicon-nitride-based PSAs are promising for the next generation of broadband optical signal processing and communication systems

The paper presents the general requirements and an exemplary design of the RF front-end system that in today4s handset is a key consumer of power. The design is required to minimize the carbon footprint in mobile handsets devices, whilst facilitating cooperation, and providing the energy-efficient operation of multi-standards for 5G communications. It provides the basis of hardware solutions for RF front-end integration challenges and offers design features covering energy efficiency for power amplifiers (PAs), Internet of Things (IoT) controlled tunable filters and compact highly isolated multiple-input and multiple-output (MIMO) antennas. An optimum design requires synergetic collaboration between academic institutions and industry in order to satisfy the key requirements of sub-6 GHz energy-efficient 5G transceivers, incorporating energy efficiency, good linearity and the potential for low-cost manufacturing. A highly integrated RF transceiver was designed and implemented to transmit and receive a picture using compact MIMO antennas integrated with efficient tunable filters and high linearity PAs. The proposed system has achieved a bit error rate (BER) of less than 10-10 at a data rate of 600 Mb/s with a wireless communication distance of more than 1 meter and power dissipation of 18-20 mW using hybrid beamforming technology and 64-QAM modulation.

An analytical load--pull-based design methodology for three-stage Doherty power amplifiers (PAs) is presented and demonstrated. A compact output combiner network, together with the input phase delays, is derived directly from transistor load--pull data and the design requirements. The technique opens up a new design space for three-stage Doherty PAs with reconfigurable high-efficiency power back-off levels. The method is designed to enable high transistor power utilization by maintaining full voltage and current swings of the main and auxiliary amplifier cells. Therefore, a wide efficiency enhancement range can be achieved also with symmetrical devices. As a proof of concept, a 2.14-GHz 30-W three-stage Doherty PA with identical gallium nitride (GaN) HEMT active devices is designed, fabricated, and characterized. The prototype PA is able to linearly reproduce 20-MHz long-term evolution signals with 8.5- and 11.5-dB peak-to-average power-ratio (PAPR), providing average efficiencies of 56.6% and 46.8% at an average output power level of 36.8 and 33.8 dBm, respectively. Moreover, an average efficiency as high as 54.5% and an average output power of 36.3 dBm have been measured at an adjacent power leakage ratio of -45.7 dBc for a 100-MHz signal with 8.5 dB of PAPR, after applying digital predistortion linearization.

This article presents an LED driver for lighting and visible light communication (VLC), which utilizes the light of the LEDs to wirelessly transmit data by modulating their instantaneous current. The solution proposed in this article seeks to unite the high efficiency of switched-mode power supplies with the wide bandwidth of linear power amplifiers (LPAs) to achieve high-speed communications. The hybrid converter processes the energy from a 48-V dc bus with an efficiency of 94% while supplying a 20-W LED load, and providing 3.68 MHz of bandwidth for VLC. Details regarding frequency limitations are provided in terms of a Laplace model. The impact of the LPA on the overall efficiency is mitigated by adopting specific design constraints. Finally, experimental results are shown from a prototype working with signals aimed at multicarrier multilevel modulations based on orthogonal frequency division multiplexing.

This communication presents a differential retrodirective array (RDA) for real-time tracking. The proposed differential RDA consists of three phase-conjugating chips and two circularly polarized antenna arrays. The phase-conjugating circuit chip which is in 0.18-um CMOS process, includes a differential low-noise amplifier, a double balanced mixer and a differential power amplifier. The specifically designed chip consumes 38.4 mW with a low voltage supply of 1.2 V. Experimental results of monostatic and bistatic cases show that, the RDA has a 3-dB beamwidth up to 77°. To the best knowledgement of the authors, the proposed RDA with circular polarization, which is promising for tracking free-moving targets, is the first differential RDA enabled by specifically designed low-cost CMOS chips.

This paper presents an ultra-low power received signal strength indicator (RSSI) amplifier circuit that can be used to detect seizures through feature extraction from electroencephalography (EEG) signals. The RSSI-based feature extraction method provides a low-power area-efficient solution for analog computing based seizure detection hardware. A 6-stage RSSI amplifier circuit was designed in 65nm CMOS technology to cover the dynamic range of EEG signals with an area of 266μm×531μm. Measurement results of the RSSI circuit show that it has a power consumption of 31.6nW, covers a 45dB dynamic range, and has a linearity error of less than ±1dB.

This article proposed a codesign of a power amplifier (PA) and a bandpass filter (BPF) named filtering PA using metal integrated and substrate integrated suspended line (MI-SISL). Two BPFs are designed separately as the input and output matching network to realize bandpass filtering response and good harmonic suppression at the same time. The BPF matching circuits are implemented using SISL-based dual-layer interdigital capacitors for miniaturization and SISL-based dual-layer spiral inductors for low loss. The suspended substrate of the PA is patterned according to the shape of the PA core circuit, which helps to reduce the circuit loss and improve efficiency. Moreover, the metal integrated technique is also proposed by replacing the top and bottom substrates of the conventional SISL structure with metal plates with good electrical and thermal conductivities for heat dissipation. A filtering PA on the MI-SISL platform at 0.9 GHz is fabricated and measured as a demonstration case. An ultrasmall size of 0.12 $λ_{{g}}$ x 0.07 $λ_{{g}}$ is achieved, where $λ_{{g}}$ is the guide wavelength at 0.9 GHz. To the best of our knowledge, this is the most compact filtering PA on the board level to date. In addition, a harmonic suppression level of 40 dBc in up to the fifth-harmonic frequency is achieved.

In this brief, a novel pseudo-differential low-transconductance amplifier is proposed based on the bootstrapping technique. The transconductor is implemented using two voltage follower topologies as amplifiers with their outputs connected to both terminals of a resistor, thus bootstrapping the voltages at these terminals to increase the equivalent resistance value, and achieve a very low transconductance without the need for large passive components. In this way, a highly-linear compact structure is designed whose transconductance can be tuned by external current sources. The circuit was fabricated in a standard 0.18μm CMOS process. The experimental results show a tunable transconductance in the range of tens of nA/V, with a total harmonic distortion lower than -40dB at 350mVpp@1kHz. The power consumption of the amplifier is 4μW under a 1.8V supply voltage. This work was supported by CONACYT through the Doctoral Grant 467255 and the Research Project CONACYT CB-2015-257985

A multi-hop free space optical link based on all-optical relays is presented. All-optical relays are either composed of simple optical amplifiers or optical regenerators. It has been shown that after a certain number of hops, the amplifier based relay cannot extend the range of the free space optical link. Therefore, we have investigated the use of a self phase modulation based regenerator as a substitute for simple amplifier based relay. By employing the regenerative relay, a 10 Gbps optical signal having pulse width of 7 ps is transmitted over a distance of 8 km of free space optical link. The free space optical link is modeled on the basis of Gamma-Gamma channel model in the strong turbulence regime. The performance of the link is observed on the basis of bit error rate analysis. It has been shown that under strong turbulence and accumulation of amplifier noise, the range of the link can only be extended by employing an optical regenerator.

This article proposes a low-complexity frequency equalization technique for pulsewidth modulation (PWM)-residual-aliasing reduction in closed-loop Class-D audio amplifiers to achieve both low total harmonic distortion plus noise (THD+N) and low quiescent current. Based on the comprehensive analysis on the phase shift delay between the audio input and the loop filter's output for the prior PWM-residual-aliasing reduction technique, the proposed technique minimizes the non-idealities via a frequency-equalization path to enhance the cancellation ability of high-frequency PWM switching components. In this way, the PWM-residual-aliasing distortion is greatly suppressed, thereby permitting Class-D audio amplifiers to achieve a further-reduced THD+N for the entire audio band while operating at a low switching frequency ( $f_{SW}$ ), leading to less quiescent current consumption. Moreover, due to the minimized phase shift delay, the required bias current of the loop filter's first operational amplifier for the target THD+N can be reduced, resulting in even lower quiescent current. Compared with other state of the arts, this work's high-fidelity second-order Class-D audio amplifier, fabricated with cost-efficient 0.5-μm CMOS technology, not only achieves a competitive minimal THD+N of 0.00091% for a 1-kHz input as well as the lowest maximal THD+N of 0.0027% over the entire audio band while operating at a low $f_{SW}$ of 168 kHz but also features both the highest figure of merit (FOM) of 2536 and the lowest quiescent current of 0.4 mA, surpassing the prior arts by a factor of 2.3.

This letter proposes a dual-band high-efficiency rectifier using a GaN transistor. Positive polarity and negative polarity modes are set at $f_{1}$ , and $f_{2}$ , respectively. Then, the rectifier operation at $f_{1}$ and $f_{2}$ is realized upon adjusting only the phase of the corresponding feedback loop. This releases the limitation that the original power amplifier (PA) must be dual-band operation. In addition, class-F harmonic control theory is used to enhance efficiency. Moreover, the proposed technique has no frequency dependence and can be used to achieve arbitrary frequency ratios. To verify the effectiveness of the proposed method, a high-efficiency rectifier operating at 1.9 and 2.4 GHz is designed and fabricated using a CGH40010F GaN HEMT. Measurements illustrate that the implemented rectifier can realize an efficiency of over 75% at 1.9 GHz and 2.4 GHz when an input power of 40 dBm is applied and the dc load is 70 Ω . Also, the size of circuit is only 4.7 cm x 3.4 cm.

This paper proposes a variable gain power amplifier (VG-PA) with stable linearity for n257/n258 frequency band applications. A switched-capacitor array is proposed in the cascode (CC) circuit to control the gain while maintaining linearity. A compensation inductor is introduced between the common-emitter (CE) and common-base (CB) transistors to suppress the phase variation. For the proof of concept, the VG-PA was fabricated in a 0.13-μm SiGe BiCMOS technology with a core size of 0.59 × 0.46 mm. Measurements show that at 24/26/28/29.5 GHz, over 5.7/5.5/7.0/7.5-dB gain tuning range, the output 1-dB compression point (OP1dB) is better than 14 dBm with OP1dB less than 1.2 dB, the third-order output intercept point (OIP3) is better than 22 dBm with OIP3 less than 3.4 dB, and the phase variation (φ) is from 3 to 9.5∘. To the author’s best knowledge, this work has the lowest linearity variation among Si-based variable gain amplifiers at millimeter-wave frequency band.

In this brief, we analyzed the output ripple in a capacitively-coupled chopper-based instrumentation amplifier (CCIA). Our analysis found that the shape and amplitude of the output ripple of the CCIA are determined by five design parameters, namely amplifier offset, transconductance, chopping frequency, Miller compensation capacitance, and the nulling resistor. With different design specifications, the CCIA ripple appears in four different shapes, including triangular ripple, RC-settling ripple, square ripple, and step-change ripple. These findings are verified by the silicon results. As the cause of each ripple shape varies, this analysis serves as a guideline for designing practical chopper-based amplifiers and their corresponding ripple reduction techniques.

The indium phosphide (InP) 130 nm double-heterojunction bipolar transistor (DHBT) offers milliwatts of output power and high signal amplification in the lower end of the terahertz frequency band when the transistor is used in a common-base configuration. Instrumentation can directly benefit from this technology by enabling the development of novel broadband sources or synthesizers that rely on our ability to amplify the signal over enormous bandwidths. However, the design of high gain and stable amplifiers presents many obstacles and limitations as we increase the bandwidth and the carrier frequency. Here we show that adding a series resistor at the collector terminal of the common-base transistor prevents instabilities in the terahertz monolithic integrated circuit (TMIC) amplifier and increases its fractional bandwidth. Adopting this technique, we report a state-of-the-art broadband common-base amplifier that exhibits a minimum small-signal gain of 18.9 dB from 325 GHz to 477 GHz. This amplifier presents the highest fractional bandwidth and gain above 300 GHz. Our work demonstrates the feasibility of high-performance amplifiers that address the need of future terahertz electronic systems.

We report a miniaturized, minimally invasive high-density neural recording interface that occupies only a 1.53 mm2 footprint for hybrid integration of a flexible probe and a 256-channel integrated circuit chip. To achieve such a compact form factor, we developed a custom flip-chip bonding technique using anisotropic conductive film and analog circuit-under-pad in a tiny pitch of 75 m. To enhance signal-to-noise ratios, we applied a reference-replica topology that can provide the matched input impedance for signal and reference paths in low-noise aimpliers (LNAs). The analog front-end (AFE) consists of LNAs, buffers, programmable gain amplifiers, 10b ADCs, a reference generator, a digital controller, and serial-peripheral interfaces (SPIs). The AFE consumes 51.92 W from 1.2 V and 1.8 V supplies in an area of 0.0161 mm2 per channel, implemented in a 180 nm CMOS process. The AFE shows > 60 dB mid-band CMRR, 6.32 Vrms input-referred noise from 0.5 Hz to 10 kHz, and 48 M input impedance at 1 kHz. The fabricated AFE chip was directly flip-chip bonded with a 256-channel flexible polyimide neural probe and assembled in a tiny head-stage PCB. Full functionalities of the fabricated 256-channel interface were validated in both in vitro and in vivo experiments, demonstrating the presented hybrid neural recording interface is suitable for various neuroscience studies in the quest of large scale, miniaturized recording systems.

In this article, a fully integrated dual-band gallium nitride (GaN) Doherty power amplifier (DPA) based on multi-resonant circuits (MRCs) is presented. A lumped T-type network in combination with the output capacitances of the main and auxiliary transistors is able to realize the quarter-wavelength transformer (QWT) in DPA, and its component values are totally decided by the operating frequency, given a certain characteristic impedance. MRCs are proposed to exhibit the required component values at two different frequencies. By replacing each component in the T-type network with an MRC, a dual-band QWT can be achieved. An integrated dual-band DPA is implemented in a commercial 0.25-μm GaN-HEMT process to validate the proposed method. The fabricated DPA shows a saturated output power of 43.8-44.7/44.4-44.8 dBm, a 6-dB back-off drain efficiency (DE) of 41%-46%/41.5%-47%, and a saturated DE of 49%-52%/56%-59% in 3.35-3.6/4.8-5.2 GHz, with a compact size of 2.8 x 3.5 mm². Applying a 100-MHz OFDM signal with a 7.8-dB peak-to-average power ratio (PAPR), an average efficiency of 37%/40% and an average power of 37/37 dBm are measured at 3.5/5.0 GHz, and the adjacent channel power ratio (ACPR) is better than -49 dBc after digital predistortion (DPD). To the best of our knowledge, the proposed DPA is the first demonstration of fully integrated dual-band GaN DPAs.

This article presents a quasi-load insensitive (QLI) Doherty power amplifier (DPA). The proposed theory makes the amplifier load insensitive in terms of output power, while its efficiency is slightly degraded for complex loads. The load insensitiveness is achieved by dynamically changing the supply voltages ( ${V_{DD}}$ ) and the input power splitting for both the carrier and peaking transistors. The optimal, load-dependent, ${V_{DD}}$ values are theoretically derived from back-off (BO) and full power conditions using load line theory. The optimal input excitation signals for the carrier and peaking devices are also derived for these variable ${V_{DD}}$ conditions. A 3.6-GHz QLI DPA was designed, and a complete system, composed of the DPA output stage, a two-channel medium power driver, an adaptive input driving stage, and a load sensing system, was implemented. The laboratory measurements have been performed for loads distributed inside a 2.0 maximum voltage standing wave ratio (VSWR) circle and show an output power variation between 43.8 and 42.6 dBm and a BO efficiency between 50% and 35%. Under modulated signal excitation, for the worst case loads, the peak output power capability of the DPA is improved from 41.7 to 43.1 dBm, and the average efficiency is increased from 32.6% to 43%.

We proposed an oversized coaxial multi-beam relativistic klystron amplifier (OCMB-RKA) with a new input coupler of lesser complexity giving enhanced input microwave power absorption rate for generating high power millimeter-wave radiation in Ka-band. The high-frequency structure of the OCMB-RKA was designed, fabricated, and cold-tested for results that agreed well with the simulated results. Furthermore, using the 3D particle-in-cell (PIC) code, the beam-wave interaction of the OCMB-RKA was simulated, considering two different materials (stainless steel and copper) making the interaction structure. When a 500 kV, 3 kA electron beam, and a focusing magnetic flux intensity of 1 T were adopted in the PIC simulation, a five-cavity OCMB-RKA yielded the output power of 610 MW at 30.525 GHz with the electronic efficiency of 40.7% and the saturated gain of 55.3 dB. Experimentally, the OCMB-RKA demonstrated its capability of generating high power Ka-band radiation typically of 390 MW power with the pulse width of 27 ns.

This paper proposes a 3rd order continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2nd order noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1st order NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

This work presents a 3-D-integrated opto-electrical receiver (RX) analog front end (AFE) operating up to 50 Gb/s. The electronic integrated circuit (EIC) is fabricated in ST SiGe BiCMOS-55-nm technology and flipped and mounted on top of the ST photonic integrated circuits (PICs) die through copper pillars (Cu-Pi). In the RX chain, a low-power fully differential shunt-feedback trans-impedance amplifier (FD SF-TIA) is exploited to reduce the input-referred noise. Following the TIA, a postamplifier (PA) based on a novel active feedback circuit topology extends the bandwidth (BW) and a buffer delivers the output electrical signal to the 100-Ω differential off-chip load. An automatic offset cancellation loop is included to protect the RX from any offset source at the input. The RX AFE consumes 56 mW from 1.8-V supply voltage and provides a trans-impedance (TI) gain of 78.7 Ω with 27-GHz BW. By exploiting the FD SF-TIA with low parasitic capacitance of the germanium photodiodes (Ge-PD) in the photonic die as well as BW recovery by the PA, the RX achieves the sensitivity of -7.5-dBm OMA at Ge-PD and -2.3-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate (BER) of

In the electronic era, the development of the transistor is unquestionably one of the most valuable contributions in the field of Electronic components. Transistor has an application to work as a switch and as an amplifier and almost in all cases. The transistor is taken as the use of an amplifier because it gives proper biasing. In this review paper, we are going to compare the Transistor as an amplifier with three configurations and select one desirable configuration with perfect amplification & that is CE configuration and taken as used in everywhere mostly.

We present a high-resolution and large dynamic range π-phase-shifted fiber Bragg grating (π-PSFBG) temperature sensor. A current modulated laser diode with a linearized optical frequency sweep is used to interrogate the sensor. The sensor is comprised of a π-PSFBG sensing head and an HCN gas cell. The gas cell functions as an absolute frequency reference to compensate for the laser frequency drift. The reflection spectrum is sent to a lock-in amplifier to generate the error signal, proportional to the first order derivative of the spectrum. The center frequency difference that carries sensing information between the π-PSFBG and HCN gas cell is calculated by cross-correlation of their error signals. A sinusoidal modulation enables to move the data processing from low-frequency stage to high-frequency stage, by phase-sensitive detection and low-pass filtering, the interferences caused by laser intensity noises and electronic devices’ noises are significantly reduced. In the experiment, a frequency resolution of 3.696 MHz with a 55 GHz mode-hop-free tuning range, is achieved, corresponding to a temperature resolution of 2.6 mK with a dynamic range from 5 to 40 °C.

This article presents a $4 \times 10$ Gb/s low-noise adaptive optical receiver, utilizing a current-reuse architecture and channel crosstalk-remove techniques in 65-nm CMOS process. The receiver integrates a transimpedance amplifier (TIA), a continuous-time linear equalizer (EQ), high-gain and high-bandwidth limiting amplifiers, and a 50- $\Omega $ output driver into a single die. The TIA employs a common-source-based pseudo-differential topology with input series inductive peaking and $g_{m}$ -enhancement to improve bandwidth and noise performance. An automatic-gain-control loop scheme is presented which solves the bandwidth variation issue caused by variation of the TIA input impedance, across a large dynamic range of a small input to a maximum overload current. Multiple crosstalk reduction techniques are adopted to improve the channel isolation performance. The 850-nm vertical cavity surface emitting laser (VCSEL)-based full-link measurement results show that the optical receiver achieves $20.4~\mu \text{A}_{\mathrm {pp}}$ sensitivity bit-error-rate (BER $ -12) with a 200-fF photodiode, competitive with other prior CMOS-based TIAs. The crosstalk over different channels is also measured, demonstrating only a sensitivity penalty of 1 dB.

This letter presents a C-band high-efficiency fully integrated high-power amplifier (HPA) monolithic microwave integrated circuit (MMIC) in 0.25 μm gallium nitride (GaN) high electron mobility transistor (HEMT) technology. The proposed GaN HPA MMIC consists of two amplifying stages, and its output stage includes 8 transistors in parallel. In order to realize the high efficiency, a low-loss harmonic control network (HCN) using a parallel LC resonate block is applied to obtain the optimum load impedance to each transistor employed in the output stage of the HPA at both f0 and 2f0. Thus, the designed GaN HPA can operate in pulse conditions of 100 μs pulse width and 10% of duty cycle over the frequency from 5.6 GHz to 6.3 GHz. The proposed high efficiency GaN HPA MMIC provides an average output power of 45.0 dBm-45.5 dBm (31.6 W-35.5 W) with a power added efficiency (PAE) of 59%-61.8%, and a gain of 26 dB-28.5 dB under a drain voltage of 28 V. The area of the proposed GaN HPA MMIC is 4.2 mm × 4 mm including pads.

This article presents an adaptive zoom-capacitance-to-digital converter (CDC)-based CMOS humidity sensor. The humidity sensor is realized by means of two differential capacitors whose dielectrics are sensitive to humidity. The sensing capacitors are interfaced with a zoom CDC, which consists of a successive-approximation-register (SAR) analog-to-digital converter (ADC) and a 3rd-order delta–sigma modulator ( $\Delta \Sigma \text{M}$ ). The SAR ADC eliminates the influence of the baseline capacitance to reduce the input range of the $\Delta \Sigma \text{M}$ . To improve the energy efficiency of the CDC across the full input range, a power-aware floating inverter amplifier (FIA) array is proposed, which is configured based on the conversion results of the SAR logic. In addition, an adaptive range-shift (ARS) zoom CDC is proposed to: 1) resist off-chip parasitics and interference and 2) allow low redundancy and a more energy-efficient FIA-based comparator, thus reducing power consumption. The proposed CMOS humidity sensor is implemented in a 0.11- $\mu \text{m}$ CMOS process. Measurement results show a capacitance resolution of 17.9 aF and an effective number of bits (ENOB) of 14.0 within a conversion time of 1.01 ms. The proposed humidity sensor consumes 1.5 $\mu \text{W}$ of power and exhibits a 0.0094 % relative humidity (RH) resolution and a ±1.5 %RH peak-to-peak accuracy (3 $\sigma $ error of 5.5 %RH) among 12 chips from 20 to 85 %RH, and it achieves a figure of merit (FoM) of 0.135 pJ $\cdot $ %RH 2 , which is more than six times better than the state of the art.

In this article, the first W-band laser-enhanced direct print additive manufacturing (LE-DPAM) monolithic microwave integrated circuit (MMIC) chip-carrier assembly is demonstrated. Acrylonitrile butadiene styrene (ABS) is 3-D printed using fused deposition modeling to form substrate layers, and DuPont CB028 conductive paste is microdispensed to form transmission lines and on-chip interconnects. These processes are combined with picosecond-pulsed laser micromachining using two wavelengths in the infrared (IR) (1064 nm) and ultraviolet (UV) (355 nm) regions to create features as small as 5 μm for printed layers with a high 6:1 aspect ratio and to improve the effective conductivity of the printed traces. The laser machining process is also adopted to fabricate vertical interconnections (vias) over multilayer substrates while also suppressing higher order modes. Four different dc-to-110-GHz transmission-line configurations have been investigated, including a coplanar waveguide (CPW), a grounded CPW (GCPW), a novel multilayer CPW-microstrip transition, and a GCPW-microstrip transition with attenuation 10 dB. This process is extended to embed a W-band MMIC low-noise amplifier (LNA) die inside a laser-machined cavity with a carrier-chip gap less than 5 μm. Also, RF/dc interconnects were microdispensed to connect the transmission lines on the substrate and MMIC die. Chip-to-board transition loss as low as 0.03 dB per interconnect with return loss >7.5 dB was achieved with performance that is comparable to that of the probed MMIC die. The MMIC chip-carrier assembly provides a low-cost, versatile yet simple on-demand laser-enhanced additive manufacturing process to package a wideband MMIC die using a single automated LE-DPAM platform.

This article presents a frontend amplifier based on the 50-μm channel length n-type only indium-tin-oxide (ITO)-stabilized ZnO thin-film transistors (TFTs) on glass substrate. The amplifier has an external-bias ac-coupled, open-loop capacitor bootstrap structure. The area and power consumption are 41 mm² and 0.1 mW (8-V supply), respectively. Electrical measurement results show a gain of 20 dB, a bandwidth of 3 Hz-6 kHz, a common-mode rejection ratio (CMRR) up to 42 dB, an input impedance of 100 MΩ , and an input-referred noise of 106 μV $_{rms}$ (integrated from 1 to 200 Hz). The noise efficiency factor (NEF) and power efficiency factor (PEF) of the amplifier are, respectively, 248 and 4.9 x 10⁵, which is comparable among the state of the arts. The amplifier is successfully used to measure the heart-rate signal, which demonstrates its practicality.

This letter presents the design of five-cell cascode distributed amplifiers (DAs) in the WIN Semiconductor PIH1-10 enhancement-mode GaAs pHEMT process. Single- and two-stage DA monolithic microwave integrated circuits (MMICs) are demonstrated, with die areas not exceeding 2.5 x 1.5 mm² and same-polarity supply and bias voltages. The cascode cells are stabilized using an RC drain-gate feedback network at the common-gate transistor of each cell, and a stability analysis is presented. All transistors have a gate width of 2 μm x 75-μm, with 750-μm total common-source gate periphery per single-stage design. The measured small-signal gain is 11.5 dB with 2.6 dB flatness and 23.2 dB with 3.2 dB flatness for the one- and two-stage amplifiers, respectively, from 10 MHz to 22 GHz. The amplifiers produce over 20-dBm output power at 3-dB gain saturation across the band.

This article presents a quadrature switched/floated capacitor power amplifier (SFCPA) with deep back-off efficiency enhancement. The SFCPA is introduced to decrease the dynamic power consumption at power back-off (PBO), which could improve the system efficiency (SE). The reconfigurable self-coupling canceling transformer (RSCCT) with enhanced tuning range of turn ratio is used to achieve impedance boosting for further improved efficiency at deep PBO. Based on the proposed SFCPA, a watt-level quadrature digital power amplifier (DPA) with IQ cell sharing, hybrid Doherty, and impedance boosting is proposed for deep PBO efficiency enhancement. Implemented in 40-nm CMOS, the proposed DPA with 1.2-/2.4-V supply achieves 30.3-dBm saturated output power ( $P_{ out}$ ) with 36.6%/32.9%/29.1%/23.7%/18.6%/13.2% SE for 0-/3-/6-/9-/12-/15-dB PBOs at 2.4 GHz. For 60-MHz 256-QAM modulation signal, it delivers 23.32-dBm average output power ( $P_{ avg}$ ) with an error vector magnitude (EVM) of -31.9 dB and an average drain efficiency (DE) of 30.7%. For 40-MHz 1024-QAM signal, it shows 20.44-dBm $P_{ avg}$ with an EVM of -35.9 dB and an average DE of 22.6%.

In this work, the performance of AlGaN/gallium nitride (GaN) high-electron mobility transistors (HEMTs) with different Fe doping tails was systematically investigated and compared. It is illustrated that the combination of the unintentionally doped (UID) GaN layer and a thinner Fe doping buffer layer would result in a faster slope rate of Fe concentration in the UID GaN layer. The devices with the fastest slope rate of Fe concentration in the UID GaN layer exhibited excellent large signal performance, including the saturated power density ( $P_{sat}$ ) of 9 W/mm and the power-added efficiency (PAE) of 65.6%. In addition, the $P_{sat}$ and the PAE of the device with the fastest slope rate of Fe concentration in UID GaN layer are 27.7% and 14.7%, which are higher than that of the device with the slowest slope rate of Fe concentration under the class AB operation conditions. Pulse I-V measurement results demonstrated that the buffer-related current collapse was more effectively suppressed in the 0.5-μm Fe doping buffer layer because of faster slope rate of Fe concentration in UID GaN layer. Moreover, the frequency-dependent capacitance and conductance measurement results indicated that the current collapse was relevant to deep traps in the UID GaN layer introduced by Fe doping. By reducing the concentration of the deep traps caused by Fe doping, the device showed excellent characteristics of dc and RF. Furthermore, controlling the Fe doping tail was important for designing the GaN-based power amplifier with high $P_{sat}$ and PAE.

A broadband terahertz amplifier waveguide module is presented. The IC chip with a width of 390 μm fits in the E-plane of a standard WR-3.4 waveguide with 20 μm air-gaps on either side. The input and output waveguide transitions integrated on the chip possess various design factors that include locations of the dipoles, back-short pedestal, and substrate vias carefully selected for near full-band characteristics. The measurements on a module containing a passive thru-line IC chip show only 2.7 dB of average loss across 220-300 GHz range. With an amplifier IC chip mounted inside, the module shows a peak gain of 17 dB at 288 GHz with a 3 dB bandwidth from 259 to 294 GHz.

One of directions of improving parameters of analog integrated circuits is a development of new and modernization of existing designs of integrated elements without significantly changing of a technological route of integrated circuit manufacturing with a simultaneous creation of new integrated elements models. The article considers the results of experimental studies of the double gate junction field-effect transistor manufactured according to the 3CBiT technological route of JSC Integral. Based on the obtained results, the electrical model of double gate junction field-effect transistor is proposed, which describes the features of its application in analog integrated circuits. Comparison of I-V characteristics of measurements results and created model simulation are presented. A small capacity and a reverse current of a double gate junction field-effect transistor top gate, an ability to compensate for the DC (direct current) component of an input current provide a significant improvement in the characteristics of analog integrated circuits such as electrometric operational amplifiers and charge-sensitive amplifiers. The developed double gate junction field-effect transistor can be used in signal readout devices required in the analog interfaces of space instrument sensors and nuclear electronics.

This paper investigates the frequency response of load modulation networks for asymmetric Doherty power amplifiers (ADPA) with an output back-off power level larger than 6 dB and a power ratio of peak to main amplifier (N − 1) larger than 1. The influence of the main path impedance transformer (IT) on the Doherty impedances at main and peak path as well as on the ADPA's efficiency is analyzed. Scaling of the main IT's characteristic impedance via ξ indicates a maximum broadband matching for an input voltage Vin of ξ · Vin,max. By weighting the frequency- and ξ-dependent efficiency curves using a probability density function (PDF), an optimum is obtained for ξ = 1/N. To verify the theory, three ADPAs with different ξ-scaled ITs are designed, measured, and compared. For the design at 3.6 GHz, a gallium nitride (GaN) transistor is used. By means of the intrinsic node matching technique, matching at the current source plane is obtained. In laboratory measurements, the ADPA with ξ = 1/N achieves a power-added efficiency (PAE) of 63% at 42 dBm output power and a PDF-weighted average PAE of 38.8% within 400 MHz bandwidth for 8 dB peak-to-average power ratio. Comparison with similar state-of-the-art ADPAs in GaN technology shows highest PAE and operation power gain GP for center frequencies larger than 3.0 GHz.

An underlapped dual-gate (U-DG) quaternary In0.05Al0.75Ga0.2N/GaN metal–oxide–semiconductor high-electron-mobility transistor (MOS-HEMT) and a conventional ternary Al0.3Ga0.7N/GaN MOS-HEMT device with the same structure are analyzed and compared by investigating their analog/radiofrequency (RF) and power performance. Quaternary InAlGaN heterostructures, having higher polarization charge density, exhibit almost three times higher two-dimensional electron gas (2DEG) concentration, thus showing 171.8% higher saturation drain current density (Id) compared with ternary AlGaN having an equal barrier width of 18 nm, at the same working voltage of 1 V, thus validating the improved analog performance. The influence of the InAlGaN barrier layer on all the performance parameters is studied by varying its thickness for three different widths (18 nm, 13 nm, and 7 nm). The 10.8% higher fT and 9.1% higher fMAX values of the InAlGaN MOS-HEMT with respect to the AlGaN counterpart prove the former’s superiority for use in high-frequency amplifiers. These percentage improvements increase to 18.3% and 54.6%, respectively, for the smaller quaternary barrier width of 7 nm. Large-signal analysis for the 7-nm InAlGaN/GaN MOS-HEMT at 100 GHz indicates a higher gain with 87.5% output power efficiency compared with 42.5% for the 18-nm AlGaN/GaN MOS-HEMT at the same input of 45 dBm, demonstrating that the thinner-barrier quaternary MOS-HEMTs is a better candidate for use in sophisticated high-power devices.

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

Integrated fiber components enable compact and robust laser systems but are usually not available with specialty fibers. However, specialty fibers allow power scaling of fiber lasers and amplifiers with all advantages of these fiber designs. In this context, chirally-coupled-core fibers show promising properties for optical fiber components. In this paper, we present the development of a highly-integrated signal and pump combiner in chirally-core-fibers using a side-pumping technology. Combining up to four fiber-coupled pump diodes, a pump-light limited power handling of 600 W can be achieved with an efficiency of 78%. The combiner was tested in a side-pumped single-frequency all-fiber amplifier but can also be implemented in almost any fiber laser or amplifier.

The charge-generating sensors are widely used in many applications in consumer, automotive and medical electronics. They generate a charge proportional to the applied input quantity: pressure, temperature, acceleration, strain, light, etc. Usually, charge amplifiers are used to register such signals. The charge amplifier is an integrator that integrates the input current over time. In continuous-time signal processing, a parallel resistor is used to dissipate the energy stored on the integration capacitor, and such self-zeroed integrator circuits are known as lossy integrators. To achieve low-frequency operation, when a capacitor is in the picofarad range, a very high-ohmic resistor, in the range of gigaohms, must be used. Such a high-ohmic resistor increases the output offset voltage to an unacceptable level. To overcome the output offset problems, a composite charge amplifier has been recently introduced. This paper presents an innovative lossy integrator readout circuit which contains only one opamp in the feedback. The circuit can be easily adapted to the needed gain and cut-off frequency. Its operation is validated by experimental results. The sufficiently low high-pass cut-off frequency allows the circuit to be used for biosignal amplification. Heart and respiration rates can be easily recorded with piezoelectric sensors attached to the wrist or lung wall. The presented circuit can benefit many applications where charge-to-voltage conversion is needed.

In bathymetric Airborne LiDAR (Light Detection And Ranging) for the measurement of various water depths, the echo of the laser signal is amplified by an amplifier circuit, the water surface is usua...

Most of the currently existed settling time design methods for the Miller-compensated two-stage operational amplifiers are based on the approximate analytical model and can obtain only inaccurate results. This paper presents an approach for the exact settling time design for this widely used circuit. By the compensation of the errors in the analytical settling behavior model and executing the conventional design procedure repeatedly, an iterative design scheme is developed. The overall errors are removed by the exact performance computation with the SPICE simulation and the accurate MOS model based sizing in the entire design process. Taking advantage of the fast convergence and precision feature of this method, an efficient process variation-aware design algorithm is further presented. Simulated design results for the amplifiers in 0.18 μm and 90 nm technology are provided to illustrate the effectiveness of the proposed method.

This paper describes a compact and low cost optically fed antenna for using as a receiver in 5G cellular networks and in distributed antenna systems. It compares the performance of two different topologies of patch antennas tightly integrated with vertical-cavity surface-emitting lasers (VCSELs), without the need for an amplifier stage or matching circuit. Opto-microwave (OM) gain of −21.5 dB at 5.15 GHz for the Microstrip patch antenna (MPA), and −24.2 dB at 4.8 GHz for the Grounded Coplanar patch antenna (GCPA) are achieved. The MPA architecture is quite original as it removes the need for RF feed lines through a direct injection of the signal from the patch to the VCSEL. The paper evaluates the different contributions to the total gain due to the VCSEL responsivity, the coupling between the optical fiber and the VCSEL, the wire-bonding losses and the antenna gain, with the goal of optimizing the steps at which major losses occur.

A microwave system in the form of a quasi-optical (QO) transmission line is proposed as an interaction circuit of an amplifier or an oscillator based on the cyclotron resonance maser (CRM) instability. The circuit consists of periodically spaced along the horizontal ${z}$ -axis focusing mirrors, which transport the Gaussian wave beam along a zigzag path with vertical and inclined segments. A beam of electrons having sufficiently high perpendicular velocities is guided by a static B-field along the ${z}$ -axis so that the e-beam periodically crosses the wave beam. The CRM instability occurs in regions where an electromagnetic wave having a Bz-component, as in a gyrotron, propagates strictly across the e-beam resulting in the interaction with minimal sensitivity to particle velocity spread. Three-dimensional Particle-In-Cell (3-D PIC) simulations demonstrate the attractiveness of this “zigzag” CRM for the implementation of relatively broadband amplifiers or oscillators with unique (more than an octave bandwidth) frequency tunability at wavelengths of 1–2 mm.

The effect of gain and embedding of amplifying cells (amp-cell) on the output power of power amplifiers (PAs) at high mm-wave frequencies is studied. This is the frequency range where matching loss becomes comparable with the gain of the amp-cell in most silicon technologies. By deriving power equations of embedded amp-cell, power contours are plotted in the gain plane and an optimum embedding is designed to maximize the output power for a desired gain. To showcase the theory, a high-frequency, high-power amp-cell, called matched cascode, is introduced and subsequently embedded to boost both power gain and output power. To increase the output power even further, a differential slot power combiner (SPC) is introduced and its equivalent circuit is analyzed. Finally, using the embedded matched cascode cell, and the SPC, a $2 \times 8$ PA is implemented in 65-nm bulk CMOS. It consumes 732 mW from 2.4-V supply voltage, with a maximum power-added efficiency (PAE) of 1.03%. The PA features a $P_{\text {sat}}$ and OP1dB of 9.4 and 6.3 dBm, respectively, at 200 GHz, and a maximum power gain of 19.5 dB.

In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

The power conversion efficiency of relativistic klystron amplifiers (RKAs) is severely limited by the strong space-charge repulsion force caused by the intense electron beam. A radial-line RKA (RL-RKA) driven by the disk beam may provide great potentials to alleviate this issue due to its radially propagating characteristic of the electron beam. However, such potential advantage of high efficiency has not been fully exploited in previous research due to the insufficient beam modulation and relatively low beam-wave coupling strength. In this article, an initial RL-RKA is improved significantly by utilizing a three-stage cascaded bunching link, a four-gap output cavity, and a lengthened drift tube. The three-stage cascaded bunching link plays a role in increasing the fundamental harmonic current and decreasing the velocity spread of the electron beam simultaneously. The four-gap output cavity is designed to improve the coupling impedance and strengthen the beam-wave power conversion. Moreover, a drift tube is lengthened suitably to boost the fundamental harmonic current further. Eventually, the power conversion efficiency of the RL-RKA is enhanced up to 67% by these measures, which indicates a significant advance over the initial state of 38%.

A high-efficiency 28 GHz/39 GHz concurrent dual-band power amplifier (PA) is proposed using the 90 nm GaAs pseudomorphic high-electron mobility transistor (pHEMT) process for the millimeter-waveband fifth generation (5G) communication application in this letter. Its high efficiency is achieved by adopting a low-loss dual-band output matching network (OMN) and employing a large power push ratio (3:1) for the driver stage and the output stage under the same bias voltage. The dual-band PA has the measured gain of 19.1 and 20.3 dB, as well as the power added efficiency (PAE) of 51.3% with the 23.8-dBm output power and 49.5% with the 23.7-dBm output power at the 3 dB compression point ( $P_{\mathrm {3\,dB}}$ ), at 29.6 and 39 GHz, respectively. The area of the proposed dual-band PA is 1.45 mm $\times1.2$ mm including pads.

In this work, we provide a framework analysis of dual-hop hybrid Millimeter Wave Radio Frequency (RF)/Free Space Optical (FSO) MIMO relaying system. The source is equipped with multiple antennas and employs conjugate beamforming while the destination consists of multiple apertures with selection combining. The system also consists of a relay operating at amplify-and-forward mode. The RF channels are subject to Nakagami-m fading while the optical links experience the M\'alaga distribution. In addition, we introduce the impairments to the relay and receiver. In fact, the relay is impaired by the High Power Amplifier (HPA) nonlinearities while the receiver suffers from the In phase and Quadrature Imbalance. Moreover, we assume two types of HPA nonlinearities impairments called Soft Envelope Limiter (SEL) and Traveling Wave Tube Amplifier (TWTA). Closed-forms of the outage probability, the bit error probability, and the ergodic capacity are derived. Capitalizing on these performances, we derive the high SNR asymptotes to unpack insightful metrics such as the diversity gain. We also address the impacts of some key factors on the system performance such as the impairments, the interferers, the number of antennas and apertures and the pointing errors, etc. Finally, the analytical expressions are confirmed by Monte Carlo simulation.