Search

This paper presents a constant-slope digital-to-time converter (CS-DTC) that leverages the concepts of constant-slope charging and charge redistribution to achieve high linearity with ultra-low power consumption (ULP) that makes the proposed DTC suitable for the Internet-of-Things (IoT) applications. The proposed CS-DTC is designed and simulated in 40-nm technology. It draws 8 μA from a 1.1 V supply when clocked at 50 MHz while achieving 3.7 ps resolution over a 7-bit range. A differential nonlinearity (DNL) and an integral nonlinearity (INL) about 0.2 LSB and 0.3 LSB, respectively, are achieved.

This paper presents a new integrated RF energy harvesting system using a rectifier with reconfigurable stages. The design replaces the diode-connected transistors used in conventional RF-DC rectifiers with diode-emulated transistors for minimizing conduction losses. In addition, a voltage feedback loop is employed to regulate the output voltage at the main load. Extra available power is provided to a secondary storage unit (supercapacitor). The system is implemented in a 130nm CMOS technology, and circuit simulations show that the proposed design achieves a peak power conversion efficiency (PCE) of 29% at 0dbm input power, and a load regulation of 10mV.

In this paper, a fully integrated reconfigurable charge pump (CP) is presented. In energy harvesting applications, the input voltage can have large variations due to change in the environmental conditions, thus the CP has to be highly reconfigurable to support a wide range of input voltages together with expected load current variations. The proposed CP offers a fractional conversion ratio in order to optimize the overall system efficiency. The analysis of the CP in terms of output resistance, optimum number of stages for a given output voltage, and efficiency is performed. A design example is shown for a 5-stage CP using a UMC 180nm CMOS technology. The CP has a programmable conversion ratio from 1.25 to 5 in steps of 0.25 to support an input voltage from 0.3V to 1.2V and an output voltage of 1.5V. The implementation uses a total on-chip pumping capacitor of 2.5nF and achieves an efficiency of more than 73% across the whole input range at a load current of 1mA.

In this paper, a fully-integrated reconfigurable dual-output energy harvesting system is introduced. The proposed energy harvesting system provides two outputs $V_{out}$ and V SC . The first output $(V_{out})$ is regulated at 1.6 V and delivers the load power in the primary mode. It is generated by the primary path of the system that is implemented using a 5-stage reconfigurable boosting charge pump. In case of having more available power than the load demand, the other output $(V_{SC})$ is used to charge a supercapacitor up to 3.2 V through a secondary path. The secondary path ensures both $V_{out}$ regulation and maximum power point tracking of the input source to optimize end-to-end efficiency of the system. The optimization algorithm used to reconfigure the system in response to the expected variations of the input available power and the load power is also presented. The proposed system is implemented in a 0.18 $\mu$m CMOS technology and uses a total on-chip flying capacitance of 2.22 nF. It achieves a maximum end-to-end efficiency of 77.3% at a total output power of 773 $\mu$W and input available power of 1 mW.

This paper presents a fully integrated power management system suited for biomedical implanted devices. The proposed system employs a reconfigurable capacitor-based step-up DC-DC converter. The proposed DC-DC converter can provide fractional voltage conversion ratio (VCR) in a step of 0.25 to support wide input range from 0.4-1.2 V providing a constant output voltage of 1.6 V. The system efficiency is optimized using a real-time monitoring for the input current supplied to the DC-DC converter. This allows the system, using a control sequence, to adaptively optimize the number of stages and switching frequency that will provide the required constant output voltage while maintaining optimum efficiency. The proposed system is designed using a 180nm CMOS technology. Simulation results show that the proposed system provides peak efficiency of 78.1%.

In this paper an automated CAD tool that can be used in integrated circuit technology characterization is proposed. The proposed methodology fills the gap found in old, as well as, new IC design methodologies. The tool allows the user to perform a rapid and full characterization for different device models available in a process design kit (PDK). A set of pre-defined suite of test-benches are created to cover different aspects of circuit design. A seamless integration of the tool in typical design environments is achieved using SKILL code and OCEAN script. Moreover, the tool can compare different PDK releases or different technologies in terms of DC/AC performance, high frequency operation, leakage, and layout area efficiency. The paper presents the tool structure, interface, and capabilities. Finally, a characterization example is applied to CMOS 130 nm technology; results are shown for different devices characterization: MOSFET, BJT, Diode, Resistor, and Capacitor.

This brief introduces a design approach for Class-AB-style ring amplifiers which differs from the design of conventional amplifiers. The theory of operation of Class-AB-style ring amplifier is discussed as well as the different design tradeoffs that affect its design. Consequently, a systematic design methodology for Class-AB-style ring amplifier is introduced. A design example of a switched-capacitor gain amplifier with a closed-loop gain of 32, using a three-stage self-biased ring amplifier, is presented. This example has been designed and implemented in UMC 130-nm CMOS technology. It achieves an spurious-free dynamic range of 72 dB with a clock frequency of 25 MHz. It operates from a single 1.2-V supply and consumes 400 $\boldsymbol \mu \text{A}$ .

This paper presents a low-power batteryless energy harvesting system for Internet of Things (IoT) applications. A dual-mode dc–dc converter is used to harvest the energy of a microscale photovoltaic (PV) transducer and provides energy, in the boost mode, to a super capacitor for storage. In the buck mode, the dc–dc converter provides energy to the load on demand. A piezoelectric transducer is used as a secondary input source to guarantee system self startup. The proposed system includes a smart control to adaptively adjust the number of sensors at the load, leading to better usage of the available energy at any given time. The implementation also includes a programmable switch sizing to optimize the overall system's efficiency for different load conditions. A maximum power point tracking is used to extract the maximum power of the PV transducer under various illumination conditions. The system has been implemented in a CMOS 130-nm technology and tested in various modes of operation. Self startup has been verified, and a peak efficiency of 90.5% has been measured.

This paper presents a novel design of an ultra-broad-band class-D power amplifier (PA). The proposed architecture is based on the concept of the ripple buck converter after employing some modifications to facilitate supporting bandwidths up to tens of MHz. The input frequency range covered using the proposed class-D PA is from 0.5MHz up to 30MHz. A wide-band transformer has been used to convert the differential outputs of the class-D PA to single-ended load. The design has been implemented and fabricated using a CMOS 0.13µm technology. It occupies an active area of 0.836mm2 and operates from a single 1.2V supply. The measurement results validates the functionality of the proposed class-D PA with good linearity and peak efficiency of 58% at 140mW of output power. This has been achieved using few off-chip passive components.

A multi-band CMOS power amplifier has been realized to be used in high-efficiency handset applications. The proposed PA is based on class-E stage linearized using envelope elimination and restoration (EER) technique. In order to cover multiple frequency bands, a wide-band passive output matching network is designed and combined with band-select feature. This allows switching between two wide-band output matching networks; increasing frequency coverage and yet satisfying the criteria of high rejection of out-of-band emissions. A design methodology is introduced to optimize the values required for the wide-band passive network. The design has been implemented using CMOS 0.13 μm technology. Simulation results show frequency coverage from 800 MHz to 2.2 GHz with peak efficiency more than 60% (before taking the effect of supply modulator) and 47% after taking the losses of the supply modulator into account. The designed EER system achieves excellent linearity performance. The test and validation process includes LTE test signal with 16 QAM modulation scheme and signal bandwidth of 20 MHz.

This paper presents an ultra-low-power receiver operating at the 2.4 GHz ISM band for internet of things (IoT) and wireless sensor nodes (WSN) applications. It complies with ZigBee 802.15.4 standard, while consuming 2.7mW from a single 1.2 voltage supply. A low-IF system architecture was chosen as a compromise between low power consumption and good performance. The receiver consists of a low-noise-amplifier (LNA), double balanced IQ mixer, complex filter, variable gain amplifier, and an analog-to-digital converter (ADC). It has been implemented in 65nm CMOS technology and occupies an active area of 0.89 mm2.

This paper presents a novel ring amplifier for continuous-time (CT) circuits. The proposed amplifier enables the usage of ring amplifier in continuous-time applications. The design parameters of the proposed architecture are discussed and analyzed. A CT second order Sigma-Delta (ΣΔ) modulator is designed using the proposed architecture achieving SNDR of 61.7 dB at signal BW of 1 MHz and sampling frequency of 104 MHz. The modulator is implemented in a 65 nm CMOS process and consumes 490 μW from a single 0.9 V power supply.

This paper introduces a modified mm-Wave push-push voltage controlled oscillator (VCO) using a double-tuned LC load. The proposed architecture, compared to the conventional push-push VCO topology, increases the power of the output signal for the same DC power by increasing the loop gain at the frequency of oscillation. The proposed 60GHz VCO design is implemented in a 65nm CMOS process and occupies an area of 0.2mm2. Simulation results show a 9dB increase in the output power, a 3.5dB improvement in the phase noise. The implemented VCO consumes 36mW of DC power from a single 1.2V supply, achieving a figure of merit (FOM) of −187.5dB. An on-chip balun is designed to provide the balanced LO signal.

This paper presents an adaptive ring amplifier that introduces a degree of freedom in speed/stabilization design trade-off in the original ring amplifier. It also introduces an area efficient solution for the auto-zeroing stability problem that the conventional ring amplifier suffers from. The proposed adaptive ring amplifier improves the linearity by 10dB at the same opera ting frequency. Moreover, it achieves a 40% improvement in the operating frequency for the same linearity and settling requirements. The proposed ring amplifier has been implemented and simulated in a low-cost CMOS 130nm technology while operating from a single 1.2V supply. It has a 98% area reduction compared to the conventional ring amplifier for the same stability conditions.1

In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-/spl mu/m BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.

A general description of nonlinearities in pseudo differential operational transconductance amplifiers (OTA) with common-mode feedback (CMFB) is introduced. The effects of CMFB nonlinearities on the differential signals are evaluated and design tradeoffs including nonidealities are determined. A practical pseudo differential fully balanced fully symmetric OTA architecture with common-mode feedforward (CMFF) is used as a case study to probe the theory. The OTA has an inherent common-mode detector; hence, the CMFB circuit is efficiently implemented. The OTA is used to implement a 100-MHz fourth-order linear-phase OTA-C filter.

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-/spl mu/m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a /spl plusmn/1.65-V power supply.

For energy harvesting applications, a power management unit (PMU) architecture operating at low input voltages is required. The most critical sub-blocks of such a PMU are the voltage multiplier and the low-voltage clock generator. An ultra-low-voltage exponential gain charge pump (ECP) that serves as a voltage multiplier for such PMUs is analyzed. A low-cost fully-integrated CMOS implementation for the ECP is proposed. Circuit simulations demonstrate a 0.85-0.90V output for input voltages as low as 150mV and static loads up to 1.5µA. The ECP was simulated in Cadence environment using a TSMC CMOS 65nm process and a total of 5nF MIM capacitors.

A low-voltage 5th-order continuous-time ΣΔ modulator for a universal mobile TV receiver is presented. A unique feature of the proposed modulator is the blocker filtering provided using a 3rd order notch filter employing frequency dependent negative resistance (FDNR). The noise added by the FDNR is shaped. The modulator employs 3-level switched-capacitor DAC in the feedback. It has been implemented in 6 5nm CMOS process and occupies an area of 0.26mm2. It consumes 6mA from a single 1.2V supply at a sampling frequency of 146MS/s while providing 70dB of dynamic range in 3.85MHz bandwidth.

An integrated digitally-controlled crystal oscillator (DCXO) is presented that generates both 38.4MHz and also a 32.768kHz real time clock (RTC) from a single 38.4MHz crystal. The DCXO can startup independently and transition seamlessly in and out of software control. The tuning range is 280ppm with 2ppb/step and guaranteed monotonicity. The phase noise is −135dBc/Hz at 1kHz offset and −146dBc/Hz at 10kHz offset. The current consumption is 5mA from a 1.4V supply in full power mode and 234µA in low power mode, including the LDO and all clock buffers. The DCXO is implemented in standard 65nm digital CMOS with a die area of 0.09mm2.

The implementation of a complete low-power microphone uplink system is presented. The system comprises a low-dropout regulator (LDO), an input operational transconductance amplifier (OTA), and a 3rd order continuous-time sigma-delta (ΣΔ) modulator. The LDO provides biasing to the microphone and OTA input. The OTA presents high input impedance to the microphone and act as a pre-amplifier. The OTA consumes 100µA from 3.3V supply and ΣΔ modulator consumes 480µA from 1.2V supply at a sampling frequency of 3MHz and achieves dynamic range of 81.5dB. A decimation filter is added after the ΣΔ modulator with decimation factor 64. The design has been implemented in 65nm CMOS process and occupies 0.25mm2.

A quad-band GSM/GPRS/EDGE receiver front-end including I and Q ADCs designed in 90nm digital CMOS technology is presented. The low band receiver designed for GSM850/GSM900 achieves 33dB gain, 1.9dB noise figure, 7.5dB of noise figure under blocking condition and -20dBm of in-band IIP3 with a power of 68mW, while the high band DCS/PCS receiver achieves 32dB gain, 2.2dB noise figure, 9.3dB of noise figure under blocking condition and -20dBm of in-band IIP3 with a power of 72mW. Total active area occupies 3mm/sup 2/.

The design of a dual-mode low-pass channel selection filter for a dual-standard 802.11b/Bluetooth direct conversion receiver is presented. The filter is an OTA-C, 5/sup th/ order, Butterworth low pass structure. The OTA is implemented as a source-degenerated bipolar differential pair. Dual-mode operation, 600 kHz cut-off frequency for Bluetooth mode and 6 MHz for Wi-Fi mode, is achieved by switching the source-degeneration resistors and the capacitors. The filter operates from a single 2.5 V supply while consuming 2.7 mA and 0.9 mA for 802.11b and Bluetooth, respectively. It achieves 10 dBm in-band IIP3, 40 dBm out-of-band IIIP3 for both modes. The measured input referred noise density is -148.92 dBV/Hz and -140.48 dBV/Hz for 802.11b and Bluetooth, respectively.

A fully integrated direct conversion receiver, supporting both Bluetooth and 802.11b standards, is implemented using IBM 0.25 /spl mu/m BiCMOS technology. The RF front-end is shared between both standards while the baseband blocks are programmable for each receiving mode. All the components of the receiver from the LNA to the ADC are integrated using 19 mm/sup 2/ of silicon area. The current consumption of the chip is 41.3 mA/45.6 mA in Bluetooth/802.11b standard and the measured sensitivity is -91 dBm/-86 dBm, respectively.

A dual-mode direct-conversion 802.11b/Bluetooth receiver is integrated from LNA to ADC in a 0.25/spl mu/m BiCMOS process. The baseband circuits are programmable to accommodate both standards while the RF front-end is shared. Die area is 21 mm/sup 2/, and the IC consumes 45.6/41.3mA (802.11b/Bluetooth). Sensitivity is -86/-91dBm and IIP3 is -13/-13dBm.

This paper presents different design considerations of active Q-enhanced LC bandpass filters. An architecture for implementing high order filters is proposed. It uses electric coupling to emulate the effect of the transformer, thus providing bandwidth tuning with small passband ripple.

This paper presents a comparative study of three single-stage high frequency linearized OTAs for the design of high-performance continuous-time filters. The advantages and disadvantages of each structure are discussed. The two pseudo-differential OTAs are suitable for very low-voltage applications. One OTA is suitable for very high frequency applications and the other one has a very large linear signal swing and a large transconductance tuning range. The third OTA is based on complementary differential pairs and has very low power consumption. Design examples and experimental results are presented to demonstrate the performance characteristics of each structure.