Search

In this letter, a sidewall-implanted trench termination for SiC devices is proposed and experimentally demonstrated. With the p-type sidewall region implemented by tilted ion implantation, the electric field crowding at the edge of the main junction can be alleviated. Compared with the conventional trench termination, devices with the fabricated sidewall-implanted trench termination exhibits a higher breakdown voltage (BV) exceeding 1800V, as well as lower leakage current. Moreover, the minimum trench width for over 1800V blocking is significantly reduced from $14~\mu \text{m}$ to $5~\mu \text{m}$. In addition, the sidewall-implanted trench termination shows stronger robustness as the dominant current path is relocated from the trench sidewall to the whole active region. [ABSTRACT FROM AUTHOR]

This article presents the design and fabrication results of the silicon carbide (SiC) super-junction Schottky barrier diode (SBD). The impact of two key device structure parameters, i.e., mesa width (MW) and trench width (TW), on the device forward and reverse performance is studied by numeric simulations and measurements. Furthermore, a simple and efficient termination structure, i.e., wide-trench termination, is proposed to protect the device edge. With this termination, the simulated device breakdown voltage is significantly increased from 1423 to 2600 V with a wide-trench termination width (WTW) larger than $20~\mu \text{m}$. The outermost MW (OMW) of the transition region is also investigated. It is found that the narrower OMW can mitigate the electric field crowding at the top of the outermost mesa and reduce the electrical stress of the dielectric. Devices with different structural parameters are fabricated and measured. The device with WTW $= 50\,\,\mu \text{m}$ and the optimum OMW demonstrates the highest breakdown voltage of 1920 V. The specific ON-resistance (${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$) of this device is 1.6 $\text{m}\Omega \cdot $ cm2. Subtracting the substrate resistance, the ${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$ is only 1.2 $\text{m}\Omega \cdot $ cm2. Such device performance successfully breaks the theoretical 1-D limit of the SiC unipolar device. Furthermore, the leakage current path of the fabricated device is investigated by thermal emission microscope (EMMI). Future improvements to reduce the leakage current are also provided. [ABSTRACT FROM AUTHOR]

For the termination in high-voltage SiC thyristor, this article proposes a single-mask implantation-free solution named aperture density modulation technique. Using this technique, the etching profile on the epitaxial layer can be controlled by the aperture layout on the mask. Thus, it can directly form the smoothly tapered junction termination extension with customizable slope profile. The experiments confirm this control ability on profiles with the extension length from 200 to 400 μm. The fabricated devices with the blocking voltage near 8 kV (~80%) demonstrate the feasibility as a termination technique. The numerical simulations present the potential to maintain this breakdown voltage within 120 μm. Therefore, a low-cost solution for high-voltage termination in SiC bipolar devices is expected using this technique. [ABSTRACT FROM AUTHOR]

Trench termination with SiO2-encapsulated dielectric for 4H-SiC devices is proposed and experimentally demonstrated. The trench is mainly refilled with spin-on dielectric which is encapsulated with SiO2to protect it from the high electric field in the trench. Such a trench termination is fabricated along with a high-voltage p-i-n diode. The fabricated device shows a repeatable breakdown voltage over 1750 V (96% of the ideal planar junction breakdown) with a termination length of $14~\mu \text{m}$ while the conventional trench termination has unrepeatable breakdown and requires over $30~\mu \text{m}$ termination length. Also, this termination length is less than ~ 1/4 of the dimension of a field limiting rings termination. Moreover, the fabrication process is robust with a large process window (Trench width ≥ 14 $\mu \text{m}$). [ABSTRACT FROM AUTHOR]

In this paper, an analytical model of insulated gate bipolar transistor (IGBT) on-state voltage ( V\mathrm {{ {{ON}}}} ) and turn-off loss ( E\mathrm {{ {{OFF}}}} ) is developed to find the optimum solution (minimum power loss) for a given application. With this model, it is found that IGBT on-state voltage is limited by the fact that holes can only flow from the anode to the cathode. The minimum on-state voltage for a Si IGBT with 110- \mu \textm wide drift region is found out to be around 0.835 V at 100 A/cm2 and room temperature. For a given operating frequency and chip size, a tradeoff between on-state voltage and turn-off loss that gives minimum device power loss can be achieved by manipulating the carrier profile in the drift region with an optimum structure design. This minimum device loss decreases mildly with increasing chip size, i.e., a merely 45% loss reduction when the chip size increases from 0.2 to 5 cm2. These results clearly indicate that the performance of an IGBT is not area sensitive. They are encouraging for device manufacturers who wish to reduce the device chip size to lower cost. However, the constraint comes from the device thermal dissipation capabilities which decrease quickly with decreasing chip size. These results are validated with numerical 2-D device simulations for a large variety of device structures, chip size, and operating frequencies (2 to 200 kHz). State-of-the-art IGBT product performance is compared against the theoretical limit indicating there is still substantial room for improvement at low and high frequencies. [ABSTRACT FROM PUBLISHER]