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Fin field-effect transistor (FinFET) scaling beyond the 10-nm node requires formation of a junction isolation region between the source and the drain to suppress sub-fin leakage current. In this paper, heavy species such as Sb and As were implanted at room temperature to form a punch-through stop (PTS) layer in ${n}$ -Ge substrates. The impact of PTS implants on channel doping and defects, as well as junction leakage, was investigated for bulk Ge ${p}$ -FinFET applications. We report retrograde doping profiles with a low surface (channel) dopant concentration of 4–5 $\times 10^{\textsf {16}}$ cm−3 for Sb PTS implants post 550 °C and 650 °C activation anneals. Besides achieving low effective channel doping, the 650 °C high-temperature activation anneal post PTS implant also helps in the reduction of channel defect density. Furthermore, low junction leakage currents are also demonstrated for Sb and As PTS implants with 550 °C and 650 °C activation anneals. To avoid damaging the FinFET channel layer due to PTS ion implantation, Ge homoepitaxy was also studied post Sb PTS implants. However, Sb PTS implants activated at 650 °C without Ge epitaxy exhibit the best results in terms of low channel dopant and defect concentrations, besides junction leakage. [ABSTRACT FROM AUTHOR]

In this paper, we present a detailed study of temperature-based ion implantation of phosphorus dopants in Ge for varying dose and anneal conditions through fabricated n+/p junctions and n-type MOSFETs (nMOSFETs). In comparison with room temperature (RT) (25 °C) and hot (400 °C) implantation, cryogenic (−100 °C) implantation with a dose of 2.2e15 \mathrmcm^-2 followed by a (400 °C) rapid thermal annealing leads to 1) lower junction leakage with higher activation energy and 2) lower sheet resistance with higher dopant activation and shallower junction depth. Gate-last Ge nMOSFETs fabricated using cryogenic implanted n+/p source/drain junction (2.2e15 \mathrmcm^-2 ) exhibit lower off-current (upto $5\times )$ and higher ON-current compared with RT (25 °C) and hot (400 °C) implanted nMOSFETs. This paper demonstrates that cryogenic implantation (−100 °C) can enable high-performance Ge nMOSFETs by alleviating the problems of lower activation and high diffusion of phosphorus in Ge. [ABSTRACT FROM PUBLISHER]