Search

Single-event upsets induced by multiple-cell charge generation are studied in a 20-nm bulk SRAM by performing laser irradiation tests. The single-pulse two-photon absorption is utilized to simulate charge generation over multiple SRAM cells. The analysis of fail bit maps reveals that the physical topology of fail bits strongly depends on data patterns stored in SRAM cells. Our results indicate that potential perturbations in multiple p-wells play a key role in determining fail bit patterns. A novel multiple-cell upset mechanism, named multi-well coupled potential unbalancing, is proposed based on the consideration of the unbalanced activation of parasitic bipolar effects. The dominance of this mechanism is confirmed through multiple-pulse irradiation tests. [ABSTRACT FROM AUTHOR]

A non-volatile memory element called a perpendicular-anisotropy magnetic tunnel junction was fabricated using CoFeB/MgO/CoFeB film stack technology. It exhibits two stable resistance values, high or low, depending on the relative directions of the magnetizations of the two ferromagnetic CoFeB layers. After being programmed into the high resistance state with a current injection scheme based on the spin transfer torque theory, the tunnel junction was exposed to 15-MeV Si ions under different voltage stress conditions. The tested structure remained in the programmed high resistance state after being bombarded with 10–100 Si ions, even under the stressed situations. A time-domain analysis proved that this result is due to the perfect immunity of the tested magnetic tunnel junction to single event upsets. Some degradation in resistance due to the heavy-ion irradiation was detected through a precise parameter analysis based on a tunneling theory but it was negligibly small (1%). There were no statistically significant changes in the thermal stability factor before and after irradiation, and this means the long-term retention properties remained unchanged. [ABSTRACT FROM PUBLISHER]

Waveforms of digital single-event transients, radiation-induced voltage transients in logic gates, can be observed by connecting two transistors to a target logic gate. Additional transistors monitor voltage transients through their drain currents, which can be measured using the conventional 50-Omega transmission-line technique widely used for measuring transient currents in single elementary transistors. Experimental results obtained in pulsed-laser irradiation tests demonstrate the validity of the observation technique and clearly reveal the pulse evolution as a function of the laser pulse energy. [ABSTRACT FROM PUBLISHER]

A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEU soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET and SEU soft-error rates at each FF distributed in logic VLSI systems. A test chip is designed using a 0.2-µm fully-depleted silicon-on-insulator standard cell library. The basic concepts have been validated with Verilog timing simulations. The cell-level implementation costs of the proposed scan FF are estimated to be reasonable. [ABSTRACT FROM AUTHOR]

Described is an estimation technique of single event transient voltage pulses in VLSI circuits from heavy-ion-induced transient currents measured in a single MOSFET. Waveforms of the transient voltage pulses are fully estimated by using transient current data obtained in various drain voltage conditions. Modeling of the irradiated device behavior for use in device/circuit simulations is not required. The concept is validated using a 2-D mixed-mode device simulation. [ABSTRACT FROM AUTHOR]