Search

Leakage current issues are worthy of attention for nonisolated grid-connected systems. This article introduces the method of eliminating common-mode (CM) voltage and reducing the leakage current based on modulation, and analyzes the correlation between actual effects of the method and the flying capacitor (FC) voltage balance in three-phase three-level FC grid-connected inverter. The proposed carrier-based modulation can balance the FC voltage by changing the transmission sequences of pulses and theoretically achieve zero CM voltage. In order to deal with the low frequency fluctuation and bias voltage of FC caused by asymmetry of actual hardware, the control method is introduced, which controls FC voltage by changing the action times’ distribution of switches, while still eliminating the CM voltage. Simulation and experimental results are provided to validate that the proposed method can control FC voltage and achieve good performance in suppressions of CM voltage, leakage, current and CM electromagnetic interference noise. [ABSTRACT FROM AUTHOR]

The increased phase number of multiphase systems enables us to exploit more degrees of freedom, such as the shape of phase carriers in pulsewidth modulation (PWM). The sawtooth carrier-based PWM (SCPWM) techniques are proposed in this article to reduce common-mode voltage (CMV) in both the peak-to-peak amplitude and the changing frequency, and it can be easily extended to symmetrical multiphase two-level inverters with any odd phase number. Theoretical analysis reveals that the switching between mirror-symmetrical carriers within one phase narrows the range of the sum of switching states in all phases, which leads to the reduction of CMV amplitude. Meanwhile, the overlapping of sawtooth carriers’ straight edges among different phases slows down the change of the sum of switching states, which results in the decrease of CMV changing frequency. Moreover, the effects of voltage harmonics injection and switches’ dead-time settings on the CMV reduction performance under the proposed SCPWM techniques are investigated. Finally, the experiment results in a five-phase induction machine and multiphase RL loads verify the improved CMV performance and the extensibility of the proposed SCPWM methods. [ABSTRACT FROM AUTHOR]

It is necessary to suppress the emission level of conducted electromagnetic interference (EMI) for the power electronics converters, and the variable switching frequency pulsewidth modulation (VSFPWM) is an alternative approach to reduce conducted EMI without adding bulky passive components. However, the experimental results indicate that many obvious EMI spikes in spectrum remain so that the conducted EMI reduction for VSFPWM is limited. In order to eliminate the EMI spikes in spectrum, this article first investigates the cause of the EMI spikes for VSFPWM, and the analysis results show that the nonuniform distribution of switching frequency is the primary reason. Then, a novel PWM strategy called uniform distribution PWM (UDPWM) is proposed to eliminate the EMI spikes and to further reduce conducted EMI. The design of a UDPWM is based on the uniform distribution of switching frequency and the principle of less switching loss. Moreover, the analytical formula of switching frequency is also deduced in detail, which adopts fixed variation range of switching frequency whatever the modulation index is. Finally, the experiments are carried out to validate the effectiveness of the UDPWM in reducing conducted EMI and switching loss. The UDPWM can approximately reduce conducted EMI by 20 dB compared with the conventional constant switching frequency PWM, and all obvious spikes in the spectrum are eliminated compared with VSFPWM. [ABSTRACT FROM AUTHOR]

Determination of high-frequency circulating current is important for coupled inductor design of paralleled voltage source inverters (VSIs). A time-domain model describing the circulating current of coupled inductor within a switching period is presented in this article. Using this model, the peak or rms values of circulating current can be calculated for different pulsewidth modulation (PWM) methods. Both the conventional 180° interleaved PWM and zero-common-mode voltage PWM algorithms are studied here. Considering the saturation nature of the magnetic cores in determining the effective inductance of coupled inductors, the variable switching frequency PWM (VSFPWM) is proposed to better utilize the coupled inductor's saturation limit, which is determined by high-frequency circulating current peak value. With the proposed strategy, both switching losses and electromagnetic interference are improved with respect to the constant switching frequency PWM. Moreover, the detailed power losses analysis of paralleled VSIs has been presented and the dynamic performance of the proposed VSFPWM has been well investigated. Finally, the proposed method has been extended to the system with 2N paralleled inverters. Detailed simulation and experimental results are provided to validate the proposed method. [ABSTRACT FROM AUTHOR]

The voltage-source inverter with pulsewidth modulation (PWM) is widely used in motor drive applications owing to the technical maturity and simplicity. However, the inverter operating in the discrete and impulse state generates the high-frequency common-mode voltage (CMV) in the neutral point terminal of stator winding, which induces the negative effects. This article proposes a CMV elimination modulation scheme for the dual two-level inverter-fed asymmetrical six-phase permanent magnet synchronous motor, which has two sets of three-phase windings spatially shifted by 30° electrical degrees. The modulation algorithm shifts the PWM signals with the designed end-to-end cyclic sequence, which can retain the zero-voltage vectors for each sub-CMV of dual three-phase windings and theoretically eliminate the total CMV for the motor drive system. The validation of the proposal is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper introduces a novel pulsewidth modulation (PWM) scheme for an open-winding permanent magnet synchronous machine (OW-PMSM) driven by dual two-level three-phase inverter with common dc bus, which can effectively deal with the inherent zero-sequence current (ZSC) problem. Based on the conventional symmetrical unipolar double-frequency sinusoidal PWM scheme with an appropriate phase shift, the common mode voltage (CMV) of two inverters remains same and cancel out each other to eliminate the modulated zero-sequence voltage (ZSV) disturbance source. In this case, the double-frequency effect can be retained to reduce the ac side current ripple and suppress both corresponding motor vibration and acoustic noise, which is advantageous to improve the synthetic performance of motor. The dc-bus voltage utilization of the novel PWM scheme is proved to reach the same maximum value comparing to the conventional modulated ZSV elimination scheme. Meanwhile, a zero-sequence controller is designed to suppress ZSC by further adjusting the two CMVs to counteract other zero-sequence disturbance sources. To verify the analysis, the proposed PWM technique associated with the control method is implemented in an OW-PMSM experimental setup to validate the superiority of the proposed method. [ABSTRACT FROM AUTHOR]

In a motor drive system, the inverter working in discrete and impulse states generates a common-mode voltage (CMV) at the terminal of the stator winding neutral point. The high-frequency CMV can induce a leakage current and a common-mode (CM) electromagnetic interference (EMI), which are potential threats to personal safety and system stability. The conventional single three-phase inverter is found to be powerless in eliminating the CMV, while the two paralleled inverters can effectively eliminate the CMV theoretically, but the three coupled inductors (CIs) should be added to the motor drive system which reduces the power density and efficiency of the system. A novel method, which associates a specially designed dual-segment three-phase motor with the CMV elimination modulation algorithm, can be utilized to cancel the extra CIs without degrading the function of the leakage current and the CM EMI suppression. The design of the dual-segment three-phase permanent magnet synchronous machine is introduced, with identical back electromotive forces for two groups of windings but with little magnetic coupling between them. Simulation and experimental results are provided to verify the validity of the proposed method in CM-related reduction and CI cancellation. Compared with the zero-CM pulsewidth modulation for paralleled inverters proposed in a previous work, the proposed dual-segment three-phase motor drive can achieve a better power density by removing the CIs. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

Paralleled inverters are not only a suitable approach to increase the power capacity, but also have the capability of common mode voltage (CMV) reduction, or even elimination. The original zero CMV modulation scheme for paralleled inverters suffers from the current jump problem in phase-leg currents. This current jump phenomenon amplifies the peak values of differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC), which is adverse for the design of coupled inductor and common-mode inductor. This paper introduces the modified modulation scheme, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents. In addition, the reduction effect of the DMCC and ZSCC can be achieved. To verify the analysis, both the simulation and experimental results are presented, which validates the proposed methods and show that they are beneficial for DMCC and ZSCC reduction. [ABSTRACT FROM AUTHOR]

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters’ phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors’ sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise. [ABSTRACT FROM PUBLISHER]