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High-speed input/output (I/O) link performance is limited by random noise as well as signal integrity issues such as dispersion, reflections, and crosstalk. Hence, accurate prediction of system performance including these random and deterministic noise is crucial in high-speed link design. This paper presents a novel, fast, and accurate method to simulate the time-domain system response. The presented method calculates the system response using multiple edge responses (MER) based on linear superposition. Being able to take into account system nonlinearity more accurately, the presented method significantly improves simulation accuracy compared with the other published fast simulation techniques based on either single bit response (SBR) or double edge responses (DER), while at the same time maintaining equivalent numerical efficiency. Furthermore, peak distortion analysis, which is commonly used to find the worst-case data pattern based on SBR, is extended for DER and MER using dynamic programming. A multiphase worst-case data pattern approach is also introduced in this paper in order to determine the worst-case system performance under both timing and voltage consideration.

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.

A new adaptation strategy of I/O link equalizers is presented based on minimizing the bit error rate (BER) as the objective function to maximize the receiver voltage margin. The adaptation strategy is verified in a 90-nm test chip on both the transmitter finite-impulse response filter (Tx-FIR) and the receiver decision-feedback equalizer (Rx-DFE). The performance is compared with the commonly used sign-sign least mean square (SS-LMS) adaptation and demonstrates significant improvements especially in the case of the Tx-FIR. This paper also demonstrates that in a highly attenuating system that contains both a Tx-FIR and Rx-DFE, using a Tx-FIR subject to peak output power constraint to compensate pre-cursor ISI is worse than solely using an Rx-DFE. The adaptation strategy is further applied to adapt the sampling phase of the clock-and-data recovery loop (CDR). The technique enables near-optimal BER performance by substantially reducing the pre-cursor ISI and requires almost no additional hardware compared to SS-LMS adaptation.

A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.

As data rate pushes to 10Gbps and beyond, timing jitter has become one of the major factors that limit the link performance. Thorough understanding of the link jitter characteristics and accurate modeling of their impact on link performance is a must even at early design stage. This paper discusses the characteristics of timing jitter in typical I/O interfaces and overviews various jitter modeling methods proposed in the literature during the past few years. Recommendations are given based on the characteristics of timing jitter and their locations.

Single-ended signaling systems, popular in memory I/O interfaces, are limited by signal and power integrity issues such as crosstalk and simultaneous switching output noise (SSO). At high data rates, the single-ended systems also suffers from random noise and timing jitter. In this paper, we present an integrated signal and power integrity simulation flow that combines statistical and transient simulation methods to enable the characterization of single-ended systems to account for random timing jitter in addition to the traditional SI issues focused on the deterministic noise such as intersymbol interference (ISI), crosstalk, and SSO noise. To include SSO noise, we co-simulate power distribution network (PDN) and channel models and treat SSO noise as another form of crosstalk. To capture any system nonlinearity, we employ time-domain based multi-edge response (MER) method to characterize the deterministic and passive portion of channels. Then, random noise and timing jitter impact are included via statistical approach. We use GDDR system to demonstrate our simulation flow.

To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the interaction between equalization adaptation and clock-data recovery (CDR), coupled with transmitter peak-power constraint. To minimize the impact of precursor ISI on the bit-error-rate (BER), we propose a new method of adapting CDR phase for maximum voltage margin.

A long chain of inverters and wire segments will amplify clock jitter and drop timing pulses due to intersymbol interference. We present a jitter attenuating buffer based on surfing techniques. Our buffer circuit consists of a few inverters with variable output strength that implement a simple, low-gain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous interfaces. Furthermore, our chains can be used to reliably transmit handshaking signals and support sliding-window protocols to improve the throughput of asynchronous communication.

We present a novel method for jointly optimizing FIR filters for pre-equalization, decision feedback equalization, and near-end crosstalk cancellation. The unified optimization problem is a linear program, and we describe sparse matrix techniques for its efficient solution. We illustrate our approach with uni- and bi-directional buses using differential signaling in both intra-board and cross-backplane scenarios.