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The next significant step in the evolution and proliferation of artificial intelligence technology will be the integration of neural network (NN) models within embedded and mobile systems. This calls for the design of compact, energy efficient NN models in silicon. In this article, we present a scalable applicationspecific integrated circuit (ASIC) design of an energy-efficient Long Short-Term Memory (LSTM) accelerator, named ELSA, which is suitable for energy-constrained devices. It includes several architectural innovations to achieve small area and high energy efficiency. To reduce the area and power consumption of the overall design, the compute-intensive units of ELSA employ approximate multiplications and still achieve high performance and accuracy. The performance is further improved through efficient synchronization of the elastic pipeline stages to maximize the utilization. The article also includes a performance model of ELSA, as a function of the hidden nodes and timesteps, permitting its use for the evaluation of any LSTM application. ELSA was implemented in register transfer level (RTL) and was synthesized and placed and routed in 65nm technology. Its functionality is demonstrated for language modeling--a common application of LSTM. ELSA is compared against a baseline implementation of an LSTM accelerator with standard functional units and without any of the architectural innovations of ELSA. The article demonstrates that ELSA can achieve significant improvements in power, area, and energy-efficiency when compared to the baseline design and several ASIC implementations reported in the literature, making it suitable for use in embedded systems and real-time applications. [ABSTRACT FROM AUTHOR]

This paper describes a fast and accurate technique to predict the steady-state throughput and the corresponding power consumption of a homogeneous multicore processor for a given benchmark workload while accounting for speed reduction due to thermal constraints. The expressions contain several parameters of interest to a system designer, like the static and dynamic-power consumptions (for hottest block and for full chip), the vertical thermal resistance of the hottest block, the leakage sensitivity to temperature, the chip threshold temperature, the ambient temperature, etc. Their computational complexity is independent of the number of cores. These are incorporated in a system-level multicore power/thermal simulator that uses the PTScalar power model and the Hotspot thermal model. The analytical throughput and power predictions were within 1.7 % of that predicted by the system-level simulator. However, the analytical technique takes less than 0.2 s for a given set of design parameters, making it well suited for early design-space exploration. In contrast, the numerical technique takes anywhere from a minute (for 4 cores) up to a few hours (for 25 cores). [ABSTRACT FROM AUTHOR]

Integrated circuits today rely on extensive reuse of IP bocks and macro cells to meet the demand for high performance system-on-chip. We propose a methodology for extracting timing models of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in device and interconnect parameters. Increasing spatial correlations in variability of the process parameters in subnanometer designs requires instance-specific characterization of these design blocks. We propose a novel technique for instance-specific calibration of precharacterized timing model. The proposed approach was evaluated on large industrial designs of 1.2- and 3.5-M gates in 65-nm technology and validated against SPICE for accuracy. [ABSTRACT FROM AUTHOR]

Fuel cell (FC) is a viable alternative power source for portable applications; it has higher energy density than traditional Li-ion battery and thus can achieve longer lifetime for the same weight or volume. However, because of its limited power density, it can hardly track fast fluctuations in the load current of digital systems. A hybrid power source, which consists of a FC and a Li-ion battery, has the advantages of long lifetime and good load following capabilities. In this paper, we consider the problem of extending the lifetime of a fuel-cell-based hybrid source that is used to provide power to an embedded system which supports dynamic voltage scaling (DVS). We propose an energy-based optimization framework that considers the characteristics of both the energy consumer (the embedded system) and the energy provider (the hybrid power source). We use this framework to develop algorithms that determine the output power level of the FC and the scaling factor of the DVS processor during task scheduling. Simulations on task traces based on a real-application (Path Finder) and a randomized version demonstrate significant superiority of our algorithms with respect to a conventional DVS algorithm which only considers energy minimization of the embedded system. [ABSTRACT FROM AUTHOR]

Variations in the interconnect geometry of nanoscale ICs translate to variations in their performance. The resulting diminished accuracy in the estimates of performance at the design stage can lead to a significant reduction in the parametric yield. Thus, determining an accurate statistical description (e.g., moments, distribution, etc.) of the interconnect's response is critical for designers. In the presence of significant variations, device or interconnect model parameters such as wire resistance, capacitance, etc., need to modeled as random variables or as spatial random processes. The corner-based analysis is not accurate, and simulations based on sampling require long computation times due to the large number of parameters or random variables. This study proposes an efficient method of computing the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by projecting the infinite series representation onto a finite dimensional subspace. The advantage of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called orthogonal polynomial expansions for response analysis (OPERA). Results from OPERA simulations on a number of design test cases match well with those from the classical Monte Carlo simulation program with integrated circuits emphasis (SPICE) and from perturbation methods. Additionally, OPERA shows good computational efficiency: speedup of up to two orders of magnitude have been observed over Monte Carlo SPICE simulations. [ABSTRACT FROM AUTHOR]