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This paper describes techniques and advances for mesh generation and refinement for the analysis of electrical package structures. After a brief review of meshing techniques, a physically based justification is provided for the basic elements of gridding required to accurately represent the following physical issues: edge-effects, projection gridding for signal return currents, conductor proximity, skin-effect, frequency effects, and dielectrics. These individual gridding components are then incorporated into a comprehensive, global algorithm. Many other meshing issues are addressed, including constraints associated with the underlying electromagnetic calculation kernel, removal of superfluous grid lines, assuring symmetric results for symmetric structures, and consistency related to causality and nonphysical effects. A number of 2D and 3D examples are taken from various codes developed by the author and novel techniques are given for effectively gridding 2D structures having even extreme geometric aspect ratios. [ABSTRACT FROM AUTHOR]

In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-en d-of- the-line (BEOL) cross section of a given technology and on a full, yet contained, description of the power-ground mesh in which the data bus is embedded. One major. aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high- frequency phenomena as the dependence of the current return- path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hard- ware measurements. [ABSTRACT FROM AUTHOR]