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Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach. [ABSTRACT FROM AUTHOR]

In a highly dynamic semiconductor manufacturing technology, the migration to the next process technology node tries to create a smaller-faster-cheaper chip. To achieve this, the integrated circuit (IC) designs are becoming more complex and new manufacturing materials/processes are introduced. Additionally, demands for sustainable yield and shorter time to volume production have to be met as they govern the profitability of the semiconductor industry. As a result, rapid yield improvement techniques are crucial to overcome huge yield losses. Any yield improvement technique typically involves detecting the yield loss (testing) and identifying its root cause (diagnosis). This paper presents a survey of the existing research work reported in the literature for test and diagnostics of nanometer chips and presents interesting open issues. [ABSTRACT FROM AUTHOR]