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Apsel4well is a monolithic active pixel sensor (MAPS) chip intended for application to fast and low material silicon vertex trackers for future experiments at high intensity machines. The design is based on a 180 nm CMOS process with quadruple well option called INMAPS. This technology makes it possible to increase the in-pixel intelligence as compared to standard three transistor MAPS and their variants. Moreover, the availability of a high resistivity epitaxial layer is confirmed to lead to further improvements in terms of charge collection performance and radiation resistance. This paper, after providing some details on the INMAPS process, focuses on the analog front-end section of the pixel readout chain. Measurement results on the main analog channel parameters, like charge sensitivity and equivalent noise charge, are given along with charge collection properties evaluation through ^90Sr/^90Y spectrum measurements and laser stimulation. Characterization data were also used for validating a TCAD model of the device. Finally, selected results from a neutron irradiation campaign with fluences up to 2.7\times 10^13 1 MeV neutron equivalent/cm^2 will be shown. [ABSTRACT FROM PUBLISHER]

This work is concerned with the design criteria and the experimental characterization of front-end electronics in a 65-nm CMOS technology for the readout of hybrid pixels and of monolithic active pixel sensors using a deep N-well as their collecting electrode. The work presents a summary of the experimental results relevant to a prototype chip, named Apsel65, focusing particularly on the front-end processor features and performance. [ABSTRACT FROM AUTHOR]

Abstract: In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/f and white noise terms is studied as a function of the main device parameters before and after exposure to 10keV X-rays and 60Co . A prototype chip designed in a 65nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced. [Copyright &y& Elsevier]

Abstract: Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper. [ABSTRACT FROM AUTHOR]

Experimental data provide insight into the mechanisms governing the impact of gate and lateral isolation dielectrics and of scaling-related technological advances on noise and its sensitivity to total ionizing dose effects in Low Power 65 nm CMOS devices. The behavior of the 1/f noise term is correlated with the effects on the drain current that irradiation brings along by turning on lateral parasitic transistors. A comparison with data from previous CMOS generations is carried out to assess the impact of process features on radiation-induced degradation effects. [ABSTRACT FROM AUTHOR]

This paper is motivated by the growing interest of the detector and readout electronics community towards silicon-on-insulator CMOS processes. Advanced SOI MOSFETs feature peculiar electrical characteristics impacting their performance with respect to bulk CMOS devices. Here we mainly focus on the study of these effects on the noise parameters of the transistors, using experimental data relevant to 180 nm fully depleted SO! devices as a reference. The comparison in terms of white and 1/f noise components with bulk MOSFETs with the same minimum feature size gives a basis of estimate for the signal-to-noise ratio achievable in detector front-end integrated circuits designed in an SO! technology. [ABSTRACT FROM AUTHOR]