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This paper presents a complete 256-electrode retinal prosthesis chip, which is small and ready for packaging and implantation. It contains 256 separate programmable drivers dedicated to 256 electrodes for flexible stimulation. A 4-wire interface is employed for power and data transmission between the chip and a driving unit. Power and forward data are recovered from a 600 kHz differential signal, while backward data are sent at 100 kbps rate simultaneously. The stimulator possesses many stimulation features, supporting various stimulation strategies. Many safety features are included such as real-time monitoring of voltage compliance and temperature, electrode self-locking in the event of out-of-compliance, and ESD protection circuit at every electrode. The chip is fabricated in a 65 nm CMOS process. The electrode driver pitch is 150 µm, and total chip area is 8 mm 2 . The chip has been extensively tested and all the requirements have been successfully verified. The measured DC current error for single driver stimulation without electrode shorting is 20 nA. The average power consumption per electrode with typical stimulus pulse parameters and full-scale output current is 129 µW, inclusive of all standby power. The chip overall power efficiency is 70% with 23 mW of power delivered to load. [ABSTRACT FROM AUTHOR]

Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved. [ABSTRACT FROM AUTHOR]