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The packing density associated with crossbar arrays offers important architectural solutions to numerous forms of computational engines. Mitigation of sneak paths in the crossbar array, however, requires additional layers in fabrication technology to impede current flow in order to avoid undesired changes to the state when reading and writing to and from the array. This results in an unavoidable increase in the vertical stacking dimension of the array. With the recent emergence of bistable memristors under both dc and ac, by adopting their asymptotic dynamics, we realize a significant improvement in memory construct and spatial constraints of memristor crossbar arrays. In this brief, we formalize a method of configuring a whole array architecture to any permutation of states without sacrificing array density by using a rigorous theoretical analysis, and confirmed via simulation. [ABSTRACT FROM AUTHOR]

This paper presents a historical review of author's early works influenced by the Circuits and Systems Group at UC Berkeley of which Prof. Ernest S. Kuh was a core member. They range from modeling of nonlinear devices and systems, in particular memristors, design optimization of satellite-based private communication networks to CMOS VLSI design and layout. [ABSTRACT FROM PUBLISHER]

In this paper, a 2 \times 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for design and analysis of n\times m passive memory arrays of memristive devices. This data-dependent 2 \times 2 model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and no limit on the memory array size. We propose self-adaptable sense resistors that can find their statistical optimum values for reading stored data patterns by composing them with either a replica of a part of resistive random access memory (RRAM) array or a part of RRAM array itself. Self-adaptable resistors can increase the average voltage detection margin by 46%, and reduce the average current consumption by 14% for the case of a 128 \times 128 passive array with off-to-on resistance ratio of 10^3. [ABSTRACT FROM PUBLISHER]

A 2 \times 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for n \times m passive memory arrays of memristive devices. The data-dependent 2 \times 2 circuit model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and has no limit on the memory array size. In addition, we propose replica-based self-adaptable sense resistors to achieve both low-power reading and large voltage detection windowing. [ABSTRACT FROM PUBLISHER]