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Device packaging techniques continue to evolve. Modern packages connect components directly using different 3-D interconnect technologies. As the 3-D interconnect density is increasing exponentially, pitches need to reduce. Current interconnect technologies available in 3-D-Stacked IC devices do not offer such high densities. Parallel front-end of line wafer processing in combination with wafer-to-wafer bonding and extreme wafer thinning steps in the 3-D System on Chip integration technology schemes enable the increase of 3-D interconnect density. During the extreme wafer thinning process pathfinding and development, different thinning techniques were evaluated to target a final Si thickness specification. In this paper, metrology use cases that were applied in this pathfinding and development phase are demonstrated. Techniques, such as wafer level interferometry, wafer edge inspection and metrology, wafer front side metrospection, and wafer high resolution topography techniques were used to investigate process issues. Metrology data enabled us to determine where the extreme wafer thinning process could be improved. The same techniques were used to validate the improvements and to monitor process stability. [ABSTRACT FROM AUTHOR]