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We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode. [ABSTRACT FROM PUBLISHER]

A new enhanced swing differential Colpitts VCO architecture enables oscillations to go beyond both the supply voltage and ground making it suitable for low voltage operation. Analysis for the oscillation frequency, differential- and common-mode oscillations, amplitude of oscillation, and start-up condition provides insight into oscillator operation and design considerations. Operating at 4.9 GHz, the VCO consumes from 1.9 mW to 3 mW for supply voltages of 400 mV and 500 mV, respectively. The 130 nm CMOS VCO's measured phase noise ranges from -132.6 to -136.2 dBc/Hz at a 3 MHz offset frequency. [ABSTRACT FROM AUTHOR]