Search

Three simulated floating inductor (SFI) circuits containing a single DDCC− called as minus‐type differential difference current conveyor are proposed. These SFIs are series lossy, parallel lossy and negative lossless ones. The used DDCC− in each of the proposed SFIs has a single Z terminal. Without needing any passive element matching constraints, each of the proposed SFIs is composed of a minimum number of passive elements. As application examples, second‐order current‐mode (CM) and voltage‐mode low‐pass (LP) filters derived from the proposed series lossy SFI are given. Also, a fourth‐order CM Butterworth LP filter example is presented as another application. A second‐order CM high‐pass (HP) filter and an RLC resonant circuit obtained from the proposed parallel lossy SFI are given. All the simulations are achieved via SPICE program. Moreover, some experimental results for the proposed lossy SFIs and CM HP filter are given in order to show the performances. [ABSTRACT FROM AUTHOR]

This paper proposes a very simple analog control for quasi-square-wave zero voltage switching (QSW-ZVS) and triangular current mode bidirectional converters. The proposed circuit controls the inductance current, thanks to the use of a variable-width hysteretic current mode control. The upper and lower bounds of the hysteretic band are clamped to ensure QSW-ZVS operation with a single current command and independently from power flow direction. This enables the control to achieve a seamless transition between source and sink modes. The advantages and disadvantages of the proposed analog control are analyzed and two different power converters are built to demonstrate the validity of this solution: a 50 W, 48 to 24 V bidirectional buck converter and a 100 W, 24 to 48 V bidirectional boost converter. [ABSTRACT FROM AUTHOR]

In this paper, a novel buck–boost converter with low electric stress on components and negative output voltage is proposed. The operational principle, steady-state analysis, and small-signal modeling of the proposed buck–boost converter in continuous conduction mode are presented. Comparisons among another five buck–boost converters and the proposed buck–boost converter are presented. It is found that the proposed converter's voltage gain is smaller than the other converters’ in step-down mode. Also, based upon the comparisons among the same kind and same number of components, the voltage and current stresses on the power switch of the proposed buck–boost converter are less than or equal to those of the comparative converters, and the voltage stress on the charge pump capacitor and the switching device power rating of the proposed buck–boost converter are always lower than those of other comparative converters. The efficiency of the proposed buck–boost converter is highest among those converters having the same number of elements. These advantages make component selection for the proposed converter much easier, and it can be used directly in applications needing a negative voltage source. Finally, simulation results and circuit experiments are given for validating the effectiveness of the proposed buck–boost converter. [ABSTRACT FROM AUTHOR]

The controller of a current-mode buck converter is realized by only time-domain circuits such as voltage-controlled oscillator (VCO), voltage-controlled delay line (VCDL), and phase detector (PD). The inductor current is sensed by a VCO, which helps improving power efficiency and eliminates the need for the slope compensation preventing the sub-harmonic oscillation. The type-II frequency compensation network is realized by a combination of VCO and VCDL without an error amplifier (EA) and RC network which may consume large power and occupy large silicon area. Instead of voltage comparator, a PD detects the error of the output voltage, which allows the switching duty cycle and thus the output voltage to be controlled in a wide range. With the proposed time-domain current-mode controller, a buck converter has been implemented in a 65-nm CMOS process. The output voltage can be regulated from 0.15 to 1.69 V from a 1.8-V input and the maximum load current is 0.6 A. The peak power efficiency is 94.9% when the output is 1.5 V and the load current is 250 mA. The load transient speed is better than 3.5 $\mu \text{s}$ for both the step-up and step-down changes of the load current by 480 mA in 0.1 $\mu \text{s}$. [ABSTRACT FROM AUTHOR]

This paper describes the design of a high-voltage amplifier for a piezoelectric transducer used in underwater communication applications, which incorporates boosting and signal generation within a single boost converter stage improving the total efficiency of the system. The proposed architecture combines hysteretic ripple current-mode control with an adaptive soft switching technique to achieve improved power efficiency over the full output power range. This is achieved by dynamically controlling the inductor current ripple to keep the converter running in soft switching. The feedback control and the soft switching regulation are implemented in a 0.25 $\mu \text{m}$ 60-V TSMC process with an external power stage. The system achieves a peak efficiency of 85% at 20 W of output power up to 30-kHz signal frequency. [ABSTRACT FROM AUTHOR]

Flyback converter is widely used in low-power adaptor applications. To achieve high efficiency for the entire load range of operations, the variable-frequency peak-current-mode (VFPCM) control is often used in the flyback converter to reduce switching frequency at light load. Since there is no small-signal model being developed for the VFPCM control to overcome the unstable problem in a wide range of operations, the present study proposes a novel, accurate small-signal model for VFPCM control operated in continuous-conduction mode. Control behavior and design are analyzed and compared with constant-frequency peak-current-mode control to give engineers insight. A control IC and a flyback converter are built for the experimental validation of the proposed model. Experimental and simulation results verify the proposed model. [ABSTRACT FROM PUBLISHER]

A new fast-response current-mode buck converter with improved $I^{2}$ -controlled techniques is presented in this paper. First, the proposed converter uses the improved $I^{2}$ -controlled techniques to design a new current-mode buck converter. The current-sensing circuit can fully sense the inductor current. The sensing current is divided into two paths; one is flown through the dynamic-acceleration circuit, and the other is transferred to hysteretic comparator to compare with dynamic-acceleration output. The $I^{2}$ -controlled techniques increase the bandwidth of the converter’s closed-loop gain that will speed up the converter’s transient response. Second, the converter uses the phase–frequency-controlled techniques to lock the switching frequency of the adaptive on-time generator of the proposed converter and reduce the difficulty of the output filter. Third, the circuit does not need slope compensation, so that it is very simple to implement. Fourth, the proposed buck converter was implemented with TSMC 0.35- $\mu \text{m}$ CMOS 2P4M processes, which is a low-cost process. The experimental results show that the maximum load current can be up to 600 mA, the input voltage range is 2.6–4 V, the output voltage is regulated at 1.8 V, the maximum power efficiency is up to 90%, and the transient response times are 2.5 and $2.8~\mu \text{s}$ at rising and falling edges, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a hybrid current mode between triangular current mode (TCM) and discontinuous current mode (DCM) in order to improve a wide-load-range efficiency for a high-frequency SiC-based boost converter. At rated load, TCM, where the zero-voltage switching (ZVS) is achieved, is used in order to increase the switching frequency and minimize the boost converter. At light load, the hybrid discontinuous current mode (HDCM), where the TCM current is flown during the zero-current interval of DCM, is applied in order to achieve both ZVS and a reduction of a current ripple. This maintains a high efficiency over a wide load range. A 1-kW prototype is realized to compare HDCM over continuous current mode (CCM), DCM, and TCM. Compared to TCM, the root-mean-square current is reduced up to 56.6% with HDCM. Consequently, the efficiency of HDCM at light load of 0.1 p.u. is improved by 3.1%. Compared to DCM, the average-current ripple in HDCM is reduced by 82.3%, whereas the efficiency of HDCM at light load of 0.1 p.u. is improved by 1.5%. Finally, when the current ripple of CCM is designed to be half of TCM, the efficiency of HDCM at rated load is improved by 0.9% compared to CCM. [ABSTRACT FROM AUTHOR]

A new adaptive current-mode control of a high step-up dc–dc converter is presented. The converter gives a very high voltage gain without using a transformer and maintains low voltage stress across the power devices. The adaptive controller is formed by combining the existing current-mode control law and an adaptive law that generates the inverse of the load resistance. The structure of the proposed adaptive law is such that the derivative of the estimate is both optimized and bounded. To facilitate the controller design, the derived averaged state-space model of the converter with parasitic elements is used. An approximate stability analysis is carried out to gain some insight into the behavior of the adaptive-controlled system. Some experimental results comparing the performance of the proposed adaptive current-mode controller with that of the existing current-mode controller are also presented. [ABSTRACT FROM PUBLISHER]

This paper presents a new buck converter with optimum-damping and dynamic-slope compensation techniques. The optimum-damping control is a well-known current control method, and the proposed dynamic-slope generator can achieve frequency compensation to prevent subharmonic oscillation. When the system is disturbed, the proposed dynamic-slope generator can stabilize the circuit in a single cycle. Hence, the dynamic-slope compensation can be used to replace traditional extra slope compensation in the optimum-damping-control circuit. The measured transient time of the load current is 2 μs from 50 to 500 mA, and 3 μs from 500 to 50 mA. The optimum-damping-control techniques can rapidly reach desired output voltage in 2–3 switching cycles. The experimental and simulation results confirm that the proposed approach can achieve the slope compensation and accelerate the transient response. The proposed converter has been fabricated with TSMC 0.18 μm CMOS 1P6M technology. The converter's operating frequency is 1 MHz, the maximum output current is 500 mA, and the peak power efficiency is 89.68% under 300-mA load current. The chip area is only 1.0376 mm × 1.0599 mm (include PADs). [ABSTRACT FROM PUBLISHER]

I2 average current mode control is a promising control technique featuring fast dynamic response, cycle-by-cycle current limiting and accurate current control. It can be treated as peak current mode control with no peak-to-average error. By combining direct current feedback and average current feedback, I 2 average current mode control is a three-loop control system. Since it is a new control technique proposed in 2013, few papers exist which discuss the small-signal model for this control method. In this paper, a small-signal model for constant frequency I2 average current mode control is proposed which successfully predicts the subharmonics oscillation when the duty cycle is close to or greater than 0.5. The characteristics of I2 average current mode control are also compared with average current mode control and peak current mode control to show its advantages. [ABSTRACT FROM AUTHOR]

While current-mode control of dc–dc converters provides numerous benefits over voltage-mode control, previous models of the control strategy have been limited to the form of classical control models. Through the use of a state-space averaged (SSA) model of current-mode control, both the open-loop and closed-loop circuit parameters of open-loop control-to-output frequency response, conducted susceptibility, input admittance, output impedance, and any other desired response can be easily obtained. In this paper, SSA models of current-mode-controlled converters are derived and presented for buck, boost, and flyback topologies operating in continuous conduction mode. The new model allows for simpler and more accurate modeling than possible with previous methods, facilitates the modeling of cascaded converters, and allows for the use of state-variable feedback and other modern control methods in applications that use current-mode control. [ABSTRACT FROM PUBLISHER]

An on-chip compensated wide output range boost converter with fixed-frequency adaptive off-time current-mode control is presented. The small signal characteristic of the boost converter with current-mode control is reviewed, and an adaptive current sensing technique is proposed to reduce the variation of phase margin at different output voltages. On-chip compensation is achieved with a Type II compensator. Adaptive off-time control is adopted for its fast response and no need for slope compensation, while its disadvantage of varying switching frequency is eliminated by the proposed off-time generator. The IC controller was fabricated in a 0.5 μm 2P3M BCD 40 V process. Measurement results confirm that an output range of 5.5 V ~ 36 V with an input voltage of 5 V is achieved. The switching frequency is fixed at 1 MHz with a variation of ±1%. The measured peak efficiency and maximum output power are 92.9% and 8.6 W, respectively. For a load step of 200 mA using a 3.3-μH inductor and a 20-μF output capacitor, overshoot and undershoot of the load transient responses are smaller than 1% of the output voltage. [ABSTRACT FROM AUTHOR]

In order to analyze the high-frequency behaviors of the peak current mode (PCM) Buck converter, a small-signal multifrequency model is proposed. The multifrequency model explains the influences from the sideband frequency components generated by the nonlinear PWM comparator. It can effectively reflect some features which cannot be shown by the conventional average model, such as the phase delay. In addition, based on the proposed model, the sample-hold effect is also introduced and analyzed in this paper. Through the derivation and validation of the new model, frequency characteristics of the PCM Buck converter can be well understood, especially in the high-frequency region. [ABSTRACT FROM AUTHOR]

A new self‐compensation technique is proposed for eliminating subharmonic oscillation and chaotic regimes in dc–dc switching converters under peak current mode control. The proposed method extracts a control signal from the error between the inductor current and a suitable reference and does not require an external signal generator as in the conventional ramp compensation scheme. The analytical expressions of the control domain using Filippov method are obtained. Simulation results show that the proposed technique can be implemented using standard analogue devices and can effectively eliminate subharmonic and chaotic oscillations and can ensure a stable operation for a wide range of the duty ratio. [ABSTRACT FROM AUTHOR]

This paper describes a complete digitally controlled dc-dc buck converter performed by field-programmable gate array (FPGA) circuitry. The voltage and current-mode control is based on a voltage control oscillator (VCO) performed measurements regarding output-voltage and inductor current, respectively. This measurement principle also uses digital-counters (digital-integrators) in order to obtain integral values for the output-voltage and inductor current. In analog current-mode control, the instantaneous inductor current-value-measurement is used for the switching action. When the VCO is used for the inductor current measurement, the integral is measured during the switching-on time set as an observation interval and the switching action occurs based on this measurement. Such a principle enables full digitalization of the voltage- and current-control loop and also the used measurement principle is capable of rejecting the switching disturbances during current and voltage measurements. All the tasks for current and voltage control were implemented within the FPGA. The algorithm was verified by simulation and experimentation at a switching-frequency of 25kHz. [ABSTRACT FROM AUTHOR]

A current-mode dc-dc converter with an on-chip current sensor is presented in this letter. The current sensor has significant improvement on the current-sensing speed. The sensing ratio of the current sensor has low sensitivity to the variation of the process, voltage, temperature and loading. The current sensor combines the sensed inductor current signal with the compensation ramp signal and the output of the error amplifier smoothly. The settling time of the current sensor is less than 10 ns. In the current-mode dc-dc converter application, the differential output of the current sensor can be directly sent to the pulse-width modulation comparator. With the proposed current sensor, the dc-dc converter could realize a low duty cycle with a high switching frequency. The dc-dc converter has been fabricated by CSMC 0.5-μm 5-V CMOS process with a die size of 2.25 mm 2. Experimental results show that the current-mode converter can achieve a duty cycle down to 0.11 with a switching frequency up to 4 MHz. The measured transient response time is less than 6 μs as the load current changes between 50 and 600 mA, rapidly. [ABSTRACT FROM AUTHOR]

This paper proposes a current-mode synthetic control (CSC) technique for the design of boost converters to overcome the difficulty in designing a current-ripple hysteresis boost converter and to maintain high conversion efficiency over a wide load range. The CSC technique has a high accuracy because of the additional voltage path through the error amplifier. A smooth load transient response is maintained when the operation transits from continuous conduction mode with a nearly constant switching frequency to discontinuous conduction mode with a load-dependent switching frequency. Generally, ripple performance, light-load efficiency, and switching frequency are traded off in the design of hysteresis control regulator. In this paper, a balance among the load-dependent switching frequencies at light loads results in high power conversion efficiency compared with conventional pulsewidth modulation converter and attains compact ripple performance. The experimental results show that the output voltage ripple can be kept <50~mV over a wide load current range from 10 to 400 mA, where as power conversion efficiency is maintained at 78% at a load current of 10 mA when the switching frequency is decreased from 5 to 2 MHz. [ABSTRACT FROM PUBLISHER]

A versatile controller architecture, used in current-mode floating buck converters for LED driving, is developed. State-of-the-art controllers rely on a fixed switching period and variable duty cycle, focusing on current averaging circuits. Instead, the proposed controller architecture is based on fixed peak current and adaptable off time as the average current control method. The control loop is comprised of an averaging block, transconductance amplifier, and an innovative time modulator. This modulator is intended to provide constant control loop response regardless of input voltage, current storage inductor, and number of LEDs in order to improve converter applicability for LED drivers. Fabricated in a 5 V standard 0.5 \mu\m CMOS technology, the prototype controller is implemented and tested in a current-mode floating buck converter. The converter exhibits sound continuous conduction mode (CCM) operation for input voltages between 11 and 20 V, and a wide inductor range of 100–1000 \mu \H. In all instances, the measured average LED current variation was lower than 10% of the desired value. A maximum conversion efficiency of 91% is obtained when driving 50 mA through four LEDs (with 14 V input voltage and an inductor of 470 \mu \H). A stable CCM converter operation is also proven by simulation for nine LEDs and 45 V input voltage. [ABSTRACT FROM AUTHOR]

This paper deepens in the study of the recently described coupled-inductor buck-boost converter. The output voltage of this dc-dc converter can be regulated above and/or below its input voltage with high efficiency and wide bandwidth. The control of the input and/or output nonpulsating converter currents is addressed in this paper. The small-signal control-to-input/output-current transfer functions in open-loop permits the design of the respective average current-mode controllers. The combination of the input- and output-current controllers with an additional output voltage limiter loop is proposed as a method to regulate one of the currents while limiting the maximum values of the other two variables. The theoretical analyses have been validated by means of simulations and also experimentally on a 48-V 800-W purpose built-prototype. In particular, the frequency response measurements that have been carried out for a representative set of the converter operating points are in good agreement with the simulations. [ABSTRACT FROM AUTHOR]

Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converter's efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15 mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3 mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97 mm. [ABSTRACT FROM AUTHOR]