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In this paper, we report on the development of a vertical wrap-gated field-effect transistor based on epitaxially grown InAs nanowires. We discuss some of the important steps involved in the growth and processing, such as nanowire position control, in situ doping, high-k dielectric deposition, spacer layer formation, and metal wrap-gate fabrication. In particular, we compare a few alternative methods for deposition of materials onto vertical structures and discuss their potential advantages and limitations. Finally, we also present a comparison of transistor performance for nanowires grown using two different epitaxial techniques. [ABSTRACT FROM AUTHOR]

We report on InAs enhancement-mode held-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-κ gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the InAs/Si conduction band offset. [ABSTRACT FROM AUTHOR]

We present electrical characterization of GaSb/InAs(Sb) nanowire tunnel field-effect transistors. The broken band alignment of the GaSb/InAs(Sb) heterostructure is exploited to allow for interband tunneling without a barrier, leading to high on-current levels. We report a maximum drive current of 310 \mu\A/\mu\m at VDS = \0.5\ \V. Devices with scaled gate oxides display transconductances up to gm = \250\ \mS/mm at VDS = \300\ \mV, which are normalized to the nanowire circumference at the axial heterojunction. [ABSTRACT FROM AUTHOR]

This letter presents dc characteristics and low-frequency noise (LFN) measurements on single vertical InAs nanowire MOSFETs with 35-nm gate length and HfO2 high-κ dielectric. The average normalized transconductance for three devices is 0.16 S/mm, with a subthreshold slope of 130 mV/decade. At 10 Hz, the normalized noise power SI/I⊃2d measures 7.3 x 10-7 Hz-1. Moreover, the material-dependent Hooge's parameter at room temperature is estimated to be 4.2 x 10-3. [ABSTRACT FROM AUTHOR]

We present results on the effects of inserting a heterostructure barrier along the channel of vertical wrapped insulator-gate field-effect transistors (WIGFETs). Two sets of devices were fabricated, one InAs WIGFET and one with a 50-nm-long InAs0.8P0.2 segment in the channel. This addition of P induces a barrier in the conduction band of 130 mV, measured from the Fermi-level. The barrier blocks the diffusion current through the channel and reduces the feedback gating of holes created from band-to-band tunneling, resulting in improvements in on/off current ratio, and subthreshold characteristics. The heterosegment also induces a shift in the threshold voltage and provides an additional parameter for threshold voltage control in nanowire III-V MOSFETs. [ABSTRACT FROM AUTHOR]

We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiOx, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiNx gate dielectrics. [ABSTRACT FROM AUTHOR]

We use crystal-phase tuning during epitaxial growth of InAs nanowires to create quantum dots with very strong confinement. A set of gate electrodes are used to reproducibly split the quantum dots into even smaller pairs for which we can control the populations down to the last electron. The double quantum dots, which are parallel-coupled to source and drain, show clear and stable odd–even level pairing due to spin degeneracy and the strong confinement. The combination of hard-wall barriers to source and drain, shallow interdot tunnel barriers, and very high single-particle excitation energies allow an order of magnitude tuning of the strength for the first intramolecular bond. We show examples for nanowires with different facet orientations, and suggest possible mechanisms behind the reproducible double-dot formation. [ABSTRACT FROM AUTHOR]

Although zinc-blende (ZB) and wurtzite (WZ) structures differ only in the atomic stacking sequence, mixing of crystal phases can strongly affect the electronic properties, a problem particularly common to bottom up-grown nanostructures. A lack of understanding of the nature of electronic transport at crystal phase junctions thus severely limits our ability to develop functional nanowire devices. In this work we investigated electron transport in InAs nanowires with designed mixing of crystal structures, ZB/WZ/ZB, by temperature-dependent electrical measurements. The WZ inclusion gives rise to an energy barrier in the conduction band. Interpreting the experimental result in terms of thermionic emission and using a drift-diffusion model, we extracted values for the WZ/ZB band offset, 135 ± 10 meV, and interface sheet polarization charge density on the order of 10-3 C/m2. The extracted polarization charge density is 1-2 orders of magnitude smaller than previous experimental results, but in good agreement with first principle calculation of spontaneous polarization in WZ InAs. When the WZ length is reduced below 20 nm, an effective barrier lowering is observed, indicating the increasing importance of tunneling transport. Finally, we found that band-bending at ZB/WZ junctions can lead to bound electron states within an enclosed WZ segment of sufficient length, evidenced by our observation of Coulomb blockade at low temperature. These findings provide critical input for modeling and designing the electronic properties of novel functional devices, such as nanowire transistors, where crystal polytypes are commonly found. [ABSTRACT FROM AUTHOR]