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A 1/3-inch 640×480-pixel CMOS image sensor was developed using a simple fixed-pattern-noise-reduction technology with a five-transistor pixel circuit and a low input-voltage I-V converter. In this report, we show the effectiveness of a low input-voltage I-V converter with a current-mirror circuit in improving the amplification ratio and linearity of a pixel circuit. The dependence of the pixel signal characteristics on the parameters of the pixel transistors was also analyzed. In a five-transistor pixel circuit, the threshold voltage of the X-Y addressing transistor affects the amplitude and level of the readout pulse. This report also contains analysis of the mechanism of the X-Y addressing transistor, illustrating the concept behind the selection of the threshold voltage.

A 1-in optical format frame-interline-transfer charge-coupled-device (FIT-CCD) image sensor with 2 million pixels and an aspect ratio of 16(H):9(V) has been developed for HDTV cameras. The effective number of pixels is 1920(H)*1036(V). In order to decrease the smear level, achieve uniform charge handling capability for the vertical CCD, and eliminate defects that appear as vertical stripes in the image of the device, aluminum wire was put onto the vertical transfer gate to decrease the resistance in the transfer gate and a dual-channel two-phase CCD was utilized for the horizontal shift register operated by a 37.125-MHz clock. As a result, this image sensor has a dynamic range of 72 dB and a sensitivity of 75 nA/lx for light with a color temperature of 2856 K. Smear is reduced to -100 dB by using the FIT-CCD image sensor structure. The horizontal limit is 1000 TV lines. In addition, image lag is negligibly small and below the sensitivity of the measurement instrument. >

The authors have developed a novel smear suppression cell structure, built with a second Al shunt process, for 1-inch optical format FIT-CCD (frame interline transfer charge-coupled device) image sensors with 2 million pixels. The first Al layer works as a photo-shield and the second one is used for V-register drive pulse wiring. With this structure, one can reduce smear levels to less than -110 dB. Moreover, one can achieve levels below -120 dB with an on-chip microlens. >

CMOS image sensors are generally characterized by their low power consumption, single power supply and capability for on-chip system integration in contrast with CCD image sensors. Even though CMOS image sensors have these advantages, they are not yet widely used in image capture applications because of their insufficient image quality due to the difficulty in FPN cancellation. This FPN-reduction technology and a hole accumulated diode (HAD) for sensing elements is applied to the CMOS image sensor. The CMOS image sensor consists of a 640/spl times/480 pixel array in 1/3 inch image format, a current-to-voltage converter, a correlated double sampling circuit and a timing generator. This image sensor uses a 0.35 /spl mu/m CMOS logic process with specialized add-on steps for HAD. The power supply is 3.3 V and maximum frame rate is 30 frames/s.

The image area of the frame FIT (frame-interline-transfer)-CCD (charge-coupled-device) image sensor is 14.0 mm (H)*7.9 mm (V), the effective number of pixels is 1920 (H)*1036 (V) and the unit cell size of a pixel is 7.3 mu m (H)*7.6 mu m (V). These specifications are for the high-definition-television (HDTV) format. The horizontal shift register consists of dual-channel, two-phase CCDs driven by a 37.125-MHz clock pulse. The readout phase of each channel is the same, which allows the reset gate of each channel to be connected together. To adapt to the 74.25-MHz readout frequency, one of the output signals is delayed by 13.47 ns through a sample-hold circuit. To reduce the voltage drop of the vertical shift register (V-CCD) drive pulse along the poly-Si transfer gate, an Al wire is put onto the transfer gate and interconnected to decrease the resistance. This Al wire works also as a photoshield. In addition, another poly-Si layer placed between the Al wire and the transfer gate prevents potential shift by separating the poly-Si contact of the transfer gate/poly-Si layer, from the Al contact of the poly-Si layer/Al wire. >

The Hole-Accumulation Diode-Sensor (HAD-Sensor) structure, which allows to implement the variable speed electronic shutter in the Interline Transfer (IT) CCD imaging sensor, has been developed. Based on this technology, a 2/3 inch imaging sensor with 420,000 picture elements for consumer, industrial, and professional use was manufactured. The theoretical lower limit of variable shutter speed is about 1/1,000,000 sec. in the case of exposure within the vertical blanking interval (i.e. below 1/787 sec.). This HAD-Sensor achieves the following five major results, which are essential to yield the variable speed electronic shutter in an IT CCD: ( 1 ) complete draining of unwanted stored charges into n-type substrate, ( 2 ) negligibly small lag, ( 3 ) dark current reduced to 1/10 of the conventional level, ( 4 ) smear reduced to 1/5 of the conventional level, and ( 5 ) increased blue sensitivity.