Search

Color filter array interpolation, also known as demosaicking and “debayering,” is a crucial process for image reconstruction in digital still cameras. This paper presents an edge-oriented demosaicking method and an efficient very-large-scale integration (VLSI) architecture for color interpolation. The design uses simple operations (addition, subtraction, shift, and comparator) and nearest neighboring pixels to catch the color difference and edges. The required line buffering of the proposed design is four lines; therefore, its hardware cost is low. Our extensive experiments revealed that the proposed technique preserved edge features and exhibited excellent quantitative evaluation and visual quality performances. Compared with the previous VLSI implementations, the proposed design achieved superior image qualities. The synthesis results revealed that by using Taiwan Semiconductor Manufacturing Company 0.18- $\mu \text{m}$ technology, the proposed design yields a processing rate of approximately 200M samples per second. [ABSTRACT FROM AUTHOR]

An efficient edge-based technique for color filter array demosaicking is presented in this paper. The proposed algorithm uses the channel information from several correlated neighboring pixels to reconstruct the missing color channels of each pixel. We employ a simple edge detector to recognize the edge direction of each processing channel by using directional color differences, and an efficient color interpolator to reconstruct the missing color channels by observing the color correlation and edge information. The proposed technique can prevent image blur and demosaicking artefacts; moreover, it has a fixed local window size and requires no previous training and no iterations. Extensive experimental results demonstrate that the proposed technique preserves edge features and performs effectively in quantitative evaluations and visual quality. The proposed algorithm has a simple computation structure; therefore, it is appropriate for real-time hardware implementation and can be used in many real-time applications. [ABSTRACT FROM PUBLISHER]

In this letter, a fast and efficient haze removal method is presented. We employ an extremum approximate method to extract the atmospheric light and propose a contour preserving estimation to obtain the transmission by using edge-preserving and mean filters alternately. Our method can efficiently avoid the halo artifact generated in the recovered image. To meet the requirement of real-time applications, an 11-stage pipelined hardware architecture for our haze removal method is presented. It can achieve 200 MHz with 12.8 K gate counts by using TSMC 0.13-\mum technology. Simulation results indicate that our design can obtain comparable results with the least execution time compared to previous algorithms and is suitable for low-cost high-performance hardware implementation for haze removal. [ABSTRACT FROM PUBLISHER]

Images are often corrupted by impulse noise in the procedures of image acquisition and transmission. In this paper, we propose an efficient denoising scheme and its VLSI architecture for the removal of random-valued impulse noise. To achieve the goal of low cost, a low-complexity VLSI architecture is proposed. We employ a decision-tree-based impulse noise detector to detect the noisy pixels, and an edge-preserving filter to reconstruct the intensity values of noisy pixels. Furthermore, an adaptive technology is used to enhance the effects of removal of impulse noise. Our extensive experimental results demonstrate that the proposed technique can obtain better performances in terms of both quantitative evaluation and visual quality than the previous lower complexity methods. Moreover, the performance can be comparable to the higher complexity methods. The VLSI architecture of our design yields a processing rate of about 200 MHz by using TSMC 0.18 μm technology. Compared with the state-of-the-art techniques, this work can reduce memory storage by more than 99 percent. The design requires only low computational complexity and two line memory buffers. Its hardware cost is low and suitable to be applied to many real-time applications. [ABSTRACT FROM PUBLISHER]

Image scaling is an important technique that is widely used in many image processing applications. This paper presents a novel scaling algorithm for the implementation of 2-D image scalar. The proposed interpolation method is based on the interpolation error theorem often mentioned in numerical analysis. A bilateral error-amender is used to make the interpolation more precise, and an edge-weighted scheme enhances the edge features of the scaled images. Extensive experimental results demonstrate that the proposed method can obtain better performance than previous methods in both quantitative evaluation and visual quality. This paper also presents an efficient very large-scale integrated architecture for the proposed method. The cooperation and hardware sharing techniques greatly reduce hardware cost requirements. Using a nine-stage pipeline, the proposed scaling circuit contains 13 k gate counts and yields a processing rate of approximately 278 MHz using TSMC 0.13-\mum technology. The hardware cost of the proposed circuit is low, making it a good candidate for high-quality image scaling applications. [ABSTRACT FROM PUBLISHER]