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This brief presents a method to map multiple concurrently executing independent tasks onto a coarse-grain reconfigurable architecture (CGRA) with adaptive frequency control to increase the overall throughput and minimize the total area. The commercial CGRA targeted in this brief is embedded as an IP into reconfigurable systems-on-a-chip and is runtime reconfigurable. It is able to reconfigure its tiles every clock cycle by loading new contexts while adapting its clock. Each tile on the CGRA is composed of a certain number of processing elements and has its own adaptive clock domain. This clock is fully adaptive so that it can match the critical path in each context and hence maximize the throughput. The method proposed in this brief effectively maps multiple independent tasks (applications) onto the same tile(s) in order to minimize the total tiles usage, requiring a smaller CGRA IP area, while achieving high throughput. Experimental results show that our method is very effective and that it can reduce the number of tiles used on average by 31.8% while degrading the overall performance by only 5.7% on average compared with the fastest solution which maps each kernel onto its own tiles with its own adaptive clock. [ABSTRACT FROM PUBLISHER]

One of the biggest advantages of C-Based VLSI design over traditional RT-level design is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. So far previous works have focuses on either pruning the design space or by creating predictive models in combination with different metaheuristics. In this letter, we present a hierarchical method which makes use of modern HLS tool’s options to synthesize functions as functional operators in order to explore these separately. Our method therefore explores each function separately and then performs a merging stage in order to obtain the overall dominating results. Moreover our proposed method detects if any changes in the behavioral description have happened between two exploration executions and only explores those functions which have been affected by the source code changes, while the results of the previous exploration are reused, thus enabling for incremental DSE. Results show that our method is very efficient. [ABSTRACT FROM PUBLISHER]

This paper presents a clustering method called clustering design space exploration (CDS-ExpA) to accelerate the architectural exploration of behavioral descriptions in C and SystemC. The trade-offs between faster exploration versus optimality of results are investigated. Two variations of CDS-ExpA were developed: CDS-ExpA(min) and CDS-ExpA(max). CDS-ExpA(min) builds the smallest possible clusters while CDS-ExpA(max) builds the largest possible ones, reducing further the design space. Results show that CDS-ExpA(min) and CDS-ExpA(max) explore the design space 90% and 92% faster on average than a previously developed annealer-based exploration, method, at the expense of not finding 36% and 47% of the Pareto optimal designs and finding the smallest design that is 7% and 9% on average, larger, and the fastest design 28% and 32% slower, respectively. [ABSTRACT FROM AUTHOR]