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Abstract: We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13nm thick with approximately 1019 cm−3 doping. Root mean square surface roughness below 1nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5×1011 cm−2 and 5.8nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti,Dy) x O y film is 35, and the off-state leakage current at −1V bias and 2.8nm equivalent oxide thickness is 5×10−7 A/cm2. We obtain a memory window of about 0.95V with ±6V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications. [Copyright &y& Elsevier]