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This research is to design an effective prefetching method required for hybrid main memory systems consisting of dynamic random-access memory (DRAM) and phase-change memory (PCM) components, which can be especially used for big data applications and massive-scale computing environment. Conventional prefetchers perform adequately for regular memory access patterns. However, graph processing applications show extremely irregular memory access characteristics, causing some difficulty in predicting accurate prefetching operation. Therefore, an effective dynamical prefetching algorithm based on the regression method is proposed in this study. We have designed an intelligent prefetch engine that can identify any dynamic accessing characteristics in memory accessing sequences. Specifically, it can select regular, linear, or polynomial regression predictive analysis based on the memory access sequence characteristics, and also dynamically determine the number of pages required for any selected prefetching. We also present a DRAM-PCM hybrid memory structure that can reduce the energy consumption and resolve the thermal issue that hampers conventional DRAM memory systems. Experimental results indicate that the performance can increase by around 40%, compared to that of conventional DRAM memory structures.

This research is to design a history table-based linear analysis method for a DRAM-PCM (phase change memory) hybrid memory system supporting irregular and complex memory accessing patterns in graph processing applications. This linear analysis method can analyze complex memory access patterns in real time through our history table structure, classifying address values requested from the LLC (last-level cache) as the prefetch candidates. Also, the proposed method is to support a prefetching operation from the storage onto the hybrid main memory, causing significant latency losses. Specifically, we proposed a new memory pattern analysis method, which is called a linear analysis based on a history table, to detect any linear memory access patterns from workloads showing irregular accessing characteristics. For the DRAM-PCM hybrid memory, dynamic data that are frequently accessed are stored in the DRAM. Thus, our linear analysis not only categorizes memory access patterns in the form of line patterns but also separates dynamic and static data so that the hybrid memory systems can be managed adaptively and efficiently. Our experiments show that our model can improve performance and energy consumption by 60% and 30%, respectively, compared to those of the traditional DRAM-only memory model. Moreover, our approach can enhance the entire system performance and energy consumption by 11.3%, 6.8%, compared to streamlined prefetcher-based models.

Processing-in-memory (PIM) architectures show the advantage of handling applications that generate complicated memory request patterns; usually, those kinds of memory streams degrade the application’s performance in conventional memory hierarchy systems. In particular, deep convolutional neural networks (DCNNs) processing that consists of several functionalities could be highly optimized if PIM cores can extend the processing capability and data accessibility. In this work, we propose a functionality-based PIM accelerator for DCNNs. We design several modules in addition to the conventional PIM system based on a hybrid memory cube (HMC). First, we compose a new buffer module, namely, a shared cache, in which PIM cores are provided DCNN functionalities and pre-trained weights. The PIM cores subsequently enhance computational utilization and data accessibility. Second, an efficient replacement method complements the shared cache to optimize the data miss rate of DCNN processing. Third, we compose dual prefetchers that can deal with DCNN’s memory access patterns, thereby reducing the system’s overall latency. Fourth, we compose a PIM scheduler for PIM core-level autonomous request control. The PIM scheduler relieves the host processor of significant computational loads, achieving the overall latency of the system and reducing the energy consumption. By the performance evaluation based on the trace-driven HMC simulator, our proposed model improves average latency and bandwidth by 38.9 and 27.9 % with only 18.7 % more energy consumption compared with conventional HMC-based PIM systems. Our system also achieves scalable processing performance because when the DCNN becomes deeper, it processes faster than conventional PIM systems.

This research proposes a memory-disk integrated system (MDIS) with pattern analysis based data management method. The proposed system consists of a pattern adaptive prefetcher with DRAM-based dual buffers and a PCM-based persistent memory structure. The PCM-based persistent memory module is exploited as conventional main memory and storage layers simultaneously. In this system, to compensate the PCMs unfavorable characteristics, a pattern analysis based prefetching method by using dual DRAM buffers with a small amount of space are designed as a sort of caching layer. The proposed pattern analysis based data management method monitors the miss rate to determine the prefetch policy, e.g., when and what to prefetch. These schemes enable flexible adaptation to the application execution characteristics showing unpredictable and inconsistent workload patterns. In order to evaluate our system, we implemented a trace-driven simulator system and launched the YCSB on Redis, Apache Storm, Apache Spark, and OpenStack Swift. The experimental result shows that the MDIS with a pattern adaptive prefetcher can reduce the total access time by 13.9% compared to the conventional scheme and thus the overall performance of the memory-disk integrated system improves.

The amount of data is increasing explosively, and many in-memory-based database management systems have been developed to efficiently manage data in real time. However, these in-memory databases mainly use DRAM main memory, which raises problems due to price and energy consumption. To mitigate these problems, we propose a hybrid main memory structure based on DRAM and NAND flash that is cheaper and consumes less energy than DRAM. The proposed system incorporates a prefetching mechanism in last-level cache based on regression analysis to handle irregular memory access from the in-memory application and a migration technique based on clustering between DRAM and NAND flash to mitigate NAND flash slow access latency, which could otherwise significantly degrade system performance. We experimentally confirmed approximately 58% and 51% execution time and energy improvement compared with using DRAM alone. We also compared existing prefetching models without migration to evaluate the proposed prefetching and migration techniques and showed approximately 24% and 23% improvement for execution time and an energy consumption, respectively.

This article presents a novel prefetching mechanism for memory-intensive workloads used in large-scale data centers. We design a negative-AND-flash/dynamic random-access memory (DRAM) hybrid memory architecture as a cost-effective memory architecture to resolve the scalability and power consumption problems of a DRAM-based model. A smart prefetching mechanism based on a cluster-management scheme to cope with dynamically varying and complex access patterns of any given application is designed for maximizing the performance of the DRAM. In this article, we propose a new concept for page management, called a cluster, which prefetches data in our hybrid memory architecture. The cluster management is based on a self-learning scheme on dynamically changeable access patterns by considering any correlation between missed pages. Experimental results show that the overall performance is significantly improved in relation to hit rate, execution time, and energy consumption. Namely, our proposed model can enhance the hit rate by 15% and reduce the execution time by 1.75 times. In addition, we can save energy consumption by around 48% by cutting the number of flushed pages to about an eighth of that in a conventional system.

In this study, we designed a KM-Cluster-based pattern adaptive prefetching mechanism for the last-level cache structure to support real time big data management. The goal is to predict future memory access patterns aggressively and accurately through a new self-learning prefetching engine model. The pattern adaptive last-level cache consisted of three major parts: the last-level cache, the first-level prefetching buffer (FLPB) and the second-level prefetching buffer (SLPB). The SLPB efficiently manages the history records of cache blocks evicted from the last-level cache through a self-learning mechanism. A K-means clustering algorithm is used as an SLPB prefetching scheme. Hybrid main memory is constructed using a small portion of the DRAM buffer space and primarily NAND-Flash memory space. The overall performance of our proposed model is evaluated for OpenStack Swift and in-memory database application-Redis. Experimental results show that the proposed architecture reduces the total execution time by 20.96% and power consumption by 31.9% compared to the same last-level cache size with no SLPB structure.

This research is to design an effective hybrid main memory structure for graph processing applications, because it is quite expensive to use only high-speed DRAM for such applications. Thus, we propose a DRAM-PCM hybrid main memory structure to reduce the cost and energy consumption and design regression prefetch scheme to cope with irregular access patterns in large graph processing workloads. In addition, the prefetch includes preprocessing algorithm to maximize prefetching performance. Our experimental evaluation shows a performance improvement of 36 percent over a conventional DRAM model, 15 percent over existing prefetch models such as GHB/PC, SMS, and AMPM, and 6 percent over the latest model.

Owing to the exponential growth of real-time data generation, the importance of stream processing is ever increasing. However, the data processing paradigm of stream processing is quite different, so it is difficult to expect high performance from memory systems applied to existing data centers. To solve this problem, two main solutions are suggested in this paper. First, a hybrid main memory and small buffer architecture are designed to reflect the execution characteristics of stream processing. Second, a hardware-based prefetch module supports correlation prefetching. Stream processing tends to accept incoming data in the main memory, so the prefetch module is used to divert data from the main memory layer to the buffer layer based on an intelligent clustering algorithm. This clustering algorithm affects the rapidly changing data access pattern of stream processing applications. By using heterogeneous main memories, not only can one enjoy the fast access latency of DRAM but also its nonvolatility, scalability, and low power consumption. The proposed hybrid memory architecture with our prefetch buffer structure can improve the buffer hit rate by 9–14% over other prefetch methods, reduce energy consumption by 26% over the conventional DRAM-only model, and achieve similar execution time over the 1/8-size DRAM space of the DRAM-only model.

Owing to the increased need for machine learning and artificial intelligence in current cloud computing systems, the amount of data that needs to be processed has exponentially increased. Thus, it is important to optimize memory and storage systems to reduce the energy consumption and execution time of applications. This paper proposes a new Q-learning-based prefetching algorithm for DRAM---NAND flash hybrid main memory architecture. To minimize the computational overheads of learning-based schemes, we have designed two learning policies, namely aggressive learning and lazy learning. The proposed system reduces the energy consumption by about 80% of the memory and storage for Redis, OpenStack Swift which is a cloud computing open source framework and Apache Storm workloads. Further, the overall execution time of workloads in cloud computing applications is reduced by almost half. Using a path generator with a Q-learning-based prefetching algorithm, we realize an increased hit rate of about 21% compared to that with a no-prefetching system, compared to non-prefetching system.

This article proposes a new phase change memory– (PCM) based memory storage architecture with associated self-adaptive data filtering for various embedded devices to support energy efficiency as well as high computing power. In this approach, PCM-based memory storage can be used as working memory and mass storage layers simultaneously, and a self-adaptive data filtering module composed of small DRAM dual buffers was designed to improve unfavorable PCM features, such as asymmetric read/write access latencies and limited endurance and enhance spatial/temporal localities. In particular, the self-adaptive data filtering algorithm enhances data reusability by screening potentially high reusable data and predicting adequate lifetime of those data depending on current victim time decision value. We also propose the possibility that a small amount of DRAM buffer is embedded into mobile processors, keeping this as small as possible for cost effectiveness and energy efficiency. Experimental results show that by exploiting a small amount of DRAM space for dual buffers and using the self-adaptive filtering algorithm to manage them, the proposed system can reduce execution time by a factor of 1.9 compared to the unified conventional model with same the DRAM capacity and can be considered comparable to 1.5× DRAM capacity.

A new storage system that integrates non-volatile with conventional memory, a harmonized memory system (HMS) for object-based cloud storage, is proposed. The system overcomes IO bottlenecks when managing large amounts of metadata and transaction logs and is composed of five modules. The first, the harmonized memory supervisor, is a translation layer for accessing the harmonized array module. It manages address translation, address mapping by page linking, and wear leveling. The second, the harmonized array module, is divided into dynamic and static areas composed of DRAM, and PCM together with NAND flash memory, respectively. The harmonized memory migration engine and data pattern predictor, which anticipates future data flow, are designed to maximize the effectiveness of the PCM array area. The harmonized logging conductor processes the log between the PCM array and NAND flash areas. Experimental results show the total execution time and energy consumption of HMS is 5.77 faster and 4.27 times lower, respectively, than the conventional DRAM-HDD model for object-based storage workloads.

In mobile computing systems, the limited amount of main memory space leads to page swap operation overhead and data duplication in both main memory and secondary storage. Furthermore, SQLite write operations in mobile devices such as smartphones and tablet PCs tend to frequently overwrite data to storage, significantly degrading performance. Thus, this article presents a unified memory-storage structure that is optimized for mobile devices and blurs the boundary between the existing main memory layer and secondary storage layer. This structure can eliminate the conventional page-swap operations that cause significant performance degradation and support fast program execution time. The unified memory-storage structure consists of a dynamic RAM (DRAM) and phase change memory (PCM) -based dual buffering module, a hybrid unified memory-storage array consisting of DRAM and NAND Flash memory, and an associated unified storage translation layer devised for the memory address and file translation mechanism as a system software module. This hybrid array of non-volatile memories is formed as a single memory-disk integrated storage space that can be logically divided into static and dynamic spaces. Experimental results show that the overall performance of the hybrid unified memory-storage system with the buffering structure increases by around 13% and power consumption is also improved by 35%, compared to current mobile system.

This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application&rsquo, s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

New nonvolatile memory devices can overcome the high-energy consumption, volatility, and density scaling limit of dynamic RAM (DRAM). With these advantages, next-generation nonvolatile memory devices can use both working memory and persistent storage simultaneously. In this study, we horizontally arrange DRAM, phase change memory (PCM), and flash memories as a single compound layer of working and storage space for a memory-disk integrated system (MDIS). The MDIS architecture consists of a static data buffer, DRAM/PCM/Flash hybrid array, and its associated MDIS management module. The static data buffer is placed between the last-level cache and DRAM/PCM/Flash hybrid array to reduce the performance gap. In the DRAM/PCM/Flash hybrid array, DRAM space and a portion of PCM space are used for dynamic data, and the remaining portion of PCM space and flash memory are used for static data including program text and data segments. Based on our simulation results, dynamic access latency of a dynamic area with 128 MB DRAM of space is faster than the MDIS with a PCM-only array model by approximately 5.5 times. Furthermore, the results show that the total execution time of our proposed model with 128-MB DRAM space improves speed by 4.3 times compared to conventional memory-storage system, respectively.

This research proposes a phase-change memory (PCM) based main memory system with an effective combination of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.

Next generation non-volatile memory technologies draw attention recently as promising candidates for replacing conventional DRAM-based memory devices. By using the favorable features such as low energy consumption, non-volatility, and good scalability, the next generation non-volatile memory devices can replace conventional main memory and secondary storage layers. This paper proposes a hot-cold data filtering adapter with it management algorithm for the memory-storage unified system which uses phase change RAM (PRAM) devices. The proposed hot-cold data filtering adapter consisting of dual decoupled adaptive buffers can improve drawbacks of PRAM, such as slower read/write access latencies and limited life time compared to DRAM, enhance spatial/temporal localities, and optimize the data reusability by analyzing data access pattern. Experimental results show that the proposed architecture and its algorithm improves the miss rate by about 69.2% and write count is decreased by 96.4% compared with a uniform buffer of the same size.

Real-time stream data processing is required to handle big data with low latency to process a large amount of incessant streaming data. We propose a clustering based inteligent prefetching scheme and its associated DRAM-PCM (phase change memory) hybrid memory management policy especially for stream processing. To alleviate stream processing's burden of requests accessing main memory, an intelligence prefetching technique is designed to reflect stream processing behavior to reduce the amount of memory access by improving buffer hit ratio. Because stream processing has to guarantee relatively small latency to the users, it is especially important for stream processsing to process the stream data in strict time. By using a hybrid memory structure, we take such advantages like high performance, low energy consumption, and memory scalability. And by using clustering based smart prefetching, we could improve buffer hit rate and because of this, overall system performance can be enhanced. Our proposed architecture and clustering based prefetching method can improve system performance by 1.15 times, compared with hybrid memory and buffer architecture without any prefetching scheme of conventional model and also energy consumption by 1.23 times, compared with DRAM only conventional model.

Next generation non-volatile memory devices are promising replacements for DRAM and Flash memories for mobile devices because of their energy efficiency and non-volatile characteristics. In this paper, we propose a new memory hierarchy system for next-generation non-volatile memory devices that is called an integrated memory-disk (IM-D) structure. It can merge a conventional main memory layer and a disk storage layer into a single memory layer using Phase change memory (PCM) and Flash memories. The IM-D architecture, consisting of a dual buffering IM-D adapter to improve the limited endurance and latencies, an array of PCM/Flash hybrid memories, and an associated memory management module called the IM-D translation layer in the operating system, is designed to utilize the advantages of next-generation non-volatile memory devices and at the same time overcome some shortcomings, like the asymmetric read/write access latencies and limited endurance, of a conventional memory hierarchy system. In the IM-D architecture, we propose an array of PCM/Flash hybrid memories and a migration scheme to enhance the cost effective performance and to reduce access latency. Our experimental results show that the miss rate of the proposed IM-D adapter is reduced by 49 % as compared with the conventional memory module, and the write count is reduced by 60.15 %. In addition, the access latency of the IM-D storage is improved by 45.3 %.

Conventional database systems manage all data on hard disks, but due to a hard disk's frequent I/O operations, this kind of management exposes critical problems when data is huge or operations are complex and frequent. As the size of the main memory continues to increase, main memory architecture and management becomes the major research trend in big data processing. Thus, we propose an optimized NAND Flash-based main memory (NFMM) structure for in-memory database systems to achieve the goal of having DRAM like performance at the lower cost and power consumption of Flash memory. For this goal, a horizontal combination of DRAM and NAND Flash memory is designed as a main memory model for database applications. A stream buffer and a DRAM buffer are designed to compensate for the slow access latency of Flash memory. Its optimized management method is designed to enhance the accessing locality and manage the stream buffer by prefetching pages. To evaluate the performance, Redis and Yahoo! Cloud Service Benchmark (YCSB) are used. In our experiment, a stream buffer is used to improve the data transfer speed. The result shows that in the proposed system, the execution time can achieve only 1.16x to 1.21x slower on average. At the same time, optimized NAND Flash-based main memory with 40 entries of stream buffer reduces power consumption up to 25% compared to the DRAM-based main memory system.

This paper presents an advanced PCM-Flash hybrid memory structure for the integrated memory-disk (IMD) structure merging the conventional main memory and disk storage into a single memory layer. The proposed structure can enhance overall write access latency of PCM (phase change memory)-Flash hybrid array and the amount of sequentially allocated data onto physical Flash memory area by applying PCM preference write policy and also designing additional page packing module. Thus, these two modules can maximize the use of PCM memory space to achieve both fast access latency and high Flash endurance by aggressively bounding adjacent pages. Thus, our advanced PCM-Flash hybrid memory structure can provide optimal performance by considering intrinsic characteristics of PCM and Flash memory devices and overcome PCM and Flash asymmetric access latency gap via PCM preference write policy. Our experimental results show that energy consumption of our advanced PCM-Flash hybrid memory structure can be improved by around 39%, and access latency can be reduced by 45%, compared to the basic model.

A new design methodology is aggressively considered on conventional memory hierarchy structure because of newly emerging non-volatile memory technologies. This paper presents a unified single memory structure that merges existing main memory layer and secondary storage layer together. This structure eliminates conventional page swap operations causing significant performance degradation and supports fast program execution time. The unified single memory structure consists of a selective data buffering module and a hybrid array of PCM (phase change memory) and NAND Flash storage. This hybrid array of non-volatile memories is formed as a single memory-disk integrated storage space which can be logically divided into static and dynamic spaces. This research is to design a selective data buffering structure to reduce asymmetric read/write latencies and increase the lifetime of hybrid storage based on PCM and NAND Flash. The proposed structure is compared with the interfacing adapter structure of the memory-disk integrated system. Experimental results show that the hit rate of the selective data buffering structure increases by 90.5%, compared with the NVPO under the memory-disk integrated system [10], which shows 76.9% hit rate. The access latency is also improved by around 20.6%.

This research is to design system software modules for main memory-disk integrated system. To utilize many useful features of recent non-volatile memory, a horizontal memory hierarchy should be considered as a new approach. Main objective of this study is to design an optimized bootstrap method for the integrated memory-disk system, along with compatibility with conventional bootloader and operating system. In this memory-disk integrated system, stored files and data are accessed in place reducing duplication between the main memory and storage. Thus, previous booting sequence of loading bootstrap and operating system from secondary storage to main memory should be changed to reflect the architectural change. Our proposed technique provides compatibility with conventional system software and fast booting time by utilizing prominent advantages of the integrated memory-disk system and optimizing booting sequence for this system. To implement this method, we modified BIOS (basic input/output system) to change booting from integrated memory-disk system. We used QEMU machine emulator to simulate the proposed booting method. Our experimental results show that the proposed bootstrap method can reduce the number of instructions to execute by around ten millions, resulting in fast boot performance and keeping the core of the bootloader.

An interfacing adapter is required between cache layer and PRAM based main memory to cover the shortcomings of PRAM. Thus this research is to design a flexible DRAM buffer (FDB) structure, which can improves performance by prefetch candidate data into FDB to reduce the miss penalty, and extends PRAM lifetime by filtering a large portion of write back data upon eviction from last level cache. Our results show that FDB can effectively minimize the access latency to achieve similar performance to the case of DRAM main memory and reduce a certain degree of write count to PRAM, thus limited endurance can get some respite thereby, typically extend their life expectancy.