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Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops and the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving upon the replacement technique in both quantum cost and ancilla inputs. We present here a further improved version of the direct feedback method. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs. We also propose the first technique for online testing of single line faults in sequential reversible circuits.

This paper presents a quantum-level realization and synthesis approach using SWAP and Fredkin (SF) gates. Our quantum realization of negative-controlled Fredkin gate requires five 2-qubit elementary quantum gates, the same as that required for realizing a positive-controlled Fredkin gate. We also propose and evaluate the performance of a synthesis approach using SF gates for realizing conservative reversible functions. Our result shows that circuit realization for conservative function using SF gates is more efficient than Toffoli gates. We achieve up to \(87\%\) improvement in gate count and quantum cost for \((4 \times 4)\) conservative reversible functions.

Ternary reversible logic functions are generally represented as ternary Galois field sum of products (TGFSOP) expressions and the TGFSOP expressions are mapped to reversible circuits using cascades of Feynman and Toffoli gates. Although a ternary logic function with a large number of variables can be minimized as a TGFSOP expression, the process is computationally expensive and the resulting reversible circuit tends to have a high quantum cost and ancilla in puts. To overcome these limitations, in this work we propose a new method of representing ternary reversible logic functions as Max of Min-terms (Max-Min) expressions, which can be mapped to a reversible circuit using multiple-controlled unary gates requiring lower quantum cost and fewer ancilla inputs. We propose a map-based minimization method for Max-Min expressions of up to four variables focusing on restrictions of the reversible circuit mapping technique.

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using emerging technologies such as quantum dot cellular automata. Earlier work uses traditional designs for sequential circuits and replaces the flip-flops and the gates with their reversible counterparts. Our earlier work used a direct feedback method without any flip-flops, which proved to be better than the replacement technique in terms of both quantum cost and ancilla inputs. This work is an improved version of our direct feedback method, which uses a different approach to the reversible mapping of sequential circuits. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs.

Ternary reversible circuits are normally realized as Toffoli cascades using ternary Galois field sum of products (TGFSOP) expressions. In this work we propose a new method for realization of ternary reversible circuits using ternary Max-Min expressions. The proposed method uses ternary multiple-controlled unary gates to map Max-Min expression into reversible circuit. We also present techniques for realizations of multiple-controlled unary gates using M-S gates at the quantum level. Preliminary results show that the proposed method produces better results than TGFSOP-based method in terms of both quantum cost and ancilla inputs.

Reversible logic is being suggested as a possibility for overcoming potential power loss and heat dissipation problems that the computing industry may soon be at a loss to overcome. However, for reversible logic to be a solution we must have techniques for synthesizing function descriptions to reversible circuits. This paper presents an improved ESOP-based reversible logic synthesis approach which leverages situations where cubes are shared by multiple outputs and ensures that the implementation of each cube requires just one Toffoli gate. It has the potential to minimize both gate count and quantum cost, and in fact our experimental results show that this technique can reduce the quantum cost up to 75% compared to results from the existing work.

Reversible computing has been theoretically shown to be an efficient approach over conventional computing. This is due to the property of virtually zero power dissipation in reversible circuits. A major concern in reversible circuits is the number of circuit lines which corresponds with qubits. Qubits are a limited resource. There are various reversible logic synthesis algorithms which require a significant number of additional constant lines. In this paper we explore the line reduction problem using a synthesis approach based on decision diagrams. We have added a sub-circuit for a positive Davio node structure to the existing node structures given in [1] with a shared node ordering in OKFDDs. OKFDDs are a combination of OBDDs and OFDDs, thus exhibiting the advantages of both. Our approach shows that the number of circuit lines and quantum cost can be reduced using OKFDDs with our new sub-circuit and shared node ordering.

In this paper we propose an approach for the design of online testable reversible circuits. A reversible circuit composed of Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. The performance of the proposed approach for detecting a single bit fault, a cross point fault and the family of missing gate faults has been observed. Discussion around the correctness of our approach and the overhead is also provided.

This paper presents a new approach for converting a ternary reversible circuit implemented from a truth table into an online testable circuit. Our approach adds three extra lines to the given circuit, inserts Feynman gates and M-S gates, and replaces the ternary Toffoli gates (KP-m gates) with TKP-(m+1) gates. Our approach works with only 2×2 gates and 1×1 gates and covers a higher number of detectable faults. Preliminary work shows fault coverage of 84.89% when the approach is applied to a testable ternary half adder.

Previous work presented a simple technique for converting an ESOP-based Boolean reversible circuit into an online testable circuit. This paper builds on the previous work by extending its application to circuits consisting of cascades of ternary Toffoli gates. The technique is applied to an existing cascade of ternary Toffoli gates, and requires that a single additional line be added to facilitate the propagation of any faults that are identified, as well as modification and/or addition of some gates. The modified circuit can detect online any single-bit errors that occur within the circuit. Experimental results compare very favourably to the only other known approach.

A new approach for online fault detection in Boolean reversible circuits is described. Previous work had described this approach for circuits generated by the basic ESOP-based logic synthesis, and in this work we extend the approach for any type of Toffoli networks. An online testable circuit is created by modifying an existing cascade of Toffoli gates in a simple process that involves changing the existing Toffoli gates as well as the addition of one line and 2p gates, where p is the number of lines in the original circuit.

Reversible logic has the potential to solve the energy efficiency problems that are beginning to create roadblocks in the continued advancement of today's computer systems. Multiple-valued versions of reversible logic can provide even further advantages, but the current literature contains very little work on testability of such designs. This paper details work on designing an online testable block for ternary reversible logic. We build on earlier work that introduced the basic design, and provide some improvements and modifications. This block implements most ternary logic operations and is capable of testing the reversible ternary network in real time (online). The block is built entirely of reversible building blocks, thus the block is itself reversible and so multiple such blocks can be combined to construct complete, testable, ternary reversible circuits.

This paper presents a simple technique to convert an ESOP-based reversible circuit into an online testable circuit. The technique does not require redesigning the whole circuit for integrating the testability feature, and no new garbage outputs are produced other than the garbage outputs needed for the ESOP-circuit. With a little extra hardware cost, the resultant circuit can detect online any single-bit errors. Experimental results show that the proposed technique can achieve an improvement of up to 58% in quantum cost and 99% in garbage outputs in average, compared to the previous work.

This paper describes three techniques for ordering ESOP cubes prior to generation of a Toffoli gate generation. Two of these techniques are from earlier work, while the third is a new approach. The new approach applies rules to manipulate the cubes followed by a reordering process. Our experiments demonstrate that the new approach is much more effective than either of the two previous approaches. We apply template matching as a post-processing step, which results in even further reductions in the number of Toffoli gates.

A revision of an ESOP-based Toffoli gate cascade synthesis technique [1] is presented. The cost metric used previously was replaced with a new cost metric based on autocorrelation coefficients to determine the placements of Toffoli gates. The algorithm remains capable of generating reversible circuits for large functions within reasonable time.

An ESOP-based Toffoli gate cascade synthesis algorithm is presented. The algorithm is capable of generating a cascade of reversible gates for logic functions with large numbers of qubits. The algorithm is fast as it uses a simple cost metric heuristic during a recursive divide-and-conquer function to determine NOT and Toffoli gate placement.

Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. We present an analysis of a basic memory element, the RS-latch, and a number of possible implementations. We then go on to introduce four reversible flip-flop designs based on the reversible RS-latch implementation.