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3-D integration using through-silicon-vias (TSVs) is emerging as one of the key technology options for continued miniaturization. However, because of increased device and current density, the reliability of the 3-D power grid and its integrity must be studied and analyzed. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. Current densities at these connections can be much higher than the expected average values, so extra care is required for accurate analysis. In prior work, TSVs are modeled as single resistors along with power grid wire segments. Such models do not capture detailed current density distribution and may miss hotspots associated with current crowding. This paper studies current crowding and its impact on 3-D power grid integrity. First, we explore the current density distribution within a TSV and its connections to the global chip power grid. Second, we implement simple TSV models to obtain current density distributions within a TSV and its local environment. These models are checked for accuracy by comparing with models simulated using finite element modeling methods. Finally, the simple TSV models are integrated with the global power grid for detailed chip-scale power analysis. more...

This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level models have been developed based on explicit expressions. The pronounced frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as skin and proximity effects. The models have been verified against numerical computations (full wave HFSS and quasi-static Q3D solvers). A dedicated test site has been designed for broadband characterization (from 1 MHz up to 110 GHz) of TSVs within a dense farm. more...

Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and power wire segments as single resistors, which cannot capture the detailed current distribution and may miss trouble spots associated with current crowding. This paper studies DC current crowding and its impact on 3D power integrity. First, we explore the current density distribution within a TSV and its power wire connections. Second, we build and validate effective TSV models for current density distributions. Finally, these models are integrated with global power wires for detailed chip-scale power grid analysis. more...

It is important to understand how to deliver power into 3D heterogeneous systems, which require different power supplies for different components (e.g., digital, analog, mixed-signal, MEMS parts). This paper reports on a study for a simplified case, where the two power supplies with different voltage levels are uniformly distributed through a TSV-based 3D system. In addition to intrinsic voltage losses along the interconnections, we investigated for the first time the power noises due to electrical couplings between the multiple power supplies. We evaluated the through-silicon-via (TSV)-based 3D power delivery networks by combining the electromagnetic (EM) and SPICE simulations. With this hybrid approach, we first partitioned the 3D system into a number of elements, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit to characterize the 3D power distribution networks. more...

While three-dimensional (3D) technology has several advantages for power delivery, an integrated chip-level, interposer-level, and package-level power distribution network in through-silicon-via (TSV)-based 3D system has to be modeled and evaluated. This paper reports on modeling of power delivery into 3D chip stacks on a silicon interposer/packaging substrate using a novel hybrid approach, i.e., combining the electromagnetic (EM) and analytic simulations. We intentionally partition the real stack-up structure of a 3D power network into separate components, i.e., package vias and traces, C-4 solders, interposer TSVs and planar wires, μ-C4 solders, chip TSVs, and on-chip power grids with node capacitors, decoupling capacitors and active current loads. All the passive RLGCs for each component are extracted using an EM simulation tool at a given working frequency point. We then assemble all the components back into a corresponding equivalent circuit model with those EM extracted RLGC values, thus to analyze the supply voltage (V dd )variation over time for 3D systems in a manner of maximum accuracy and efficiency. more...

Decoupling capacitors are essential to reduce high transient current noise and to provide a low impedance power delivery path. 3D technology has several advantages for power delivery, and this work investigates the impacts of decoupling capacitors on through-silicon-via (TSV)-based 3D power networks using a novel hybrid modeling approach, i.e., combining electromagnetic (EM) and SPICE simulations. We first partitioned a 3D system into a number of components, extracted the RLGC parasitics for each decomposed physical element, and imported them into an assembled system-level equivalent circuit. Through comparing and analyzing the effectiveness of several decoupling strategies, design tradeoffs are made in selecting the proper values and placement of decoupling capacitors to ensure optimal power distribution solution in 3D architectures. more...

3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache memory is one potential application of 3DI [2]. This work describes the design and operation of a prototype of a 3D system, constructed by stacking a memory layer, built with eDRAM [3] and logic blocks from the IBM Power7™ processor L3 cache, and a “processor proxy” layer in 45nm CMOS technology [4] enhanced to include through-silicon vias (TSVs) [5]. Unlike the previously reported 3D eDRAM [6], the 3D stack described here is constructed using 50μm pitch μC4's joining the front side of one thick chip to TSV connections on the back side of a thinned chip. TSVs are formed of Cu-filled vias that are ∼20μm in diameter and more...

The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V. more...