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In this paper, we discuss the advantages and opportunities presented by high-speed ( $>$ 50 GHz) reconfigurable integrated circuits and how they may drive reconfigurable systems applications, such as software-defined radio, radar, and imaging. We propose silicon–germanium (SiGe) BiCMOS as an example technology that enables ultrafast reconfigurable systems and present several circuit designs based on SiGe heterojunction bipolar transistors (HBTs) . We compare circuit designs between generations of IBM's SiGe process, including a recent 9HP process featuring devices with a cutoff frequency $(f_{T} ) $ of 300 GHz. We describe an architecture for an 8-b 80-Gs/s analog-to-digital converter (ADC and a 48 $\times$ 48 cell field-programmable gate array (FPGA), which provide powerful solutions for useful functions, such as digital signal processing (DSP) and polyphase filtering. Other circuit concepts are described, including a voltage-controlled oscillator (VCO) with a tuning range of 26 GHz and a high-performance (80 Gb/s) crossbar switch, which provide utility in reconfigurable system applications. Measured results from fabricated implementations of these described systems are presented. We comment on future prospects of these systems and examine an emerging lateral bipolar device ( $f_{T}=$ 825 GHz) having 100 $\times$ less power consumption than conventional vertical HBTs.

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5–10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic blocks (CLBs) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. More routing capabilities are provided with more inputs/outputs in each direction than similar designs. A chip consisting of four FPGA ring oscillators was fabricated. The Spice simulation results and chip measurements are presented.

This paper describes the implementation of a scalable SiGe FPGA that serves as an interleaving and deinterleaving block in a high-speed reconfigurable data acquisition system. In this paper, the different generations of SiGe configurable blocks (Basic Cells(BC)) evolved from the Xilinx 6200 are presented and measured. The latest generation has a 94% reduction in power consumption (from 71 to 4.2mW) and an 82.5% reduction of the propagation delay (from 238 to 42 ps) compared to the first generation design. To demonstrate the SiGe FPGA's capabilities of handling gigahertz signals, the SiGe FPGAs configured as the 4:1 multiplexer and 1:4 demultiplexer were designed to run at 10 Gbps. The comparisons between the SiGe and CMOS FPGAs are also provided. With these design results, the SiGe FPGA is able to process gigahertz signals such as S and K microwave bands.

FPGAs have been a popular topic among electrical engineers for over a decade. Modern FPGAs are denser, faster and use less power compared to PLD and CPLD. This paper presents a high speed FPGA that operates in the gigahertz range. An improved reconfigurable circuit is described. State-of-the-art IBM SiGe BiCMOS technology is used to realize this high speed FPGA. A measurement on a fabricated chip proves that this FPGA is capable of operating at 11 GHz, a SONET OC-192 standard, for optical applications.

This paper describes the implementation of a scalable SiGe FPGA that serves as a high speed FPGA test platform. A new configurable block (Basic Cell) has been evolved from the Xilinx 6200 specification, and is designed to perform in the gigahertz range. Two chips, a 4:1 multiplexer and 1:4 demultiplexer, were designed using the IBM SiGe 7HP process. The two designs can process 10 Gbps data streams.

The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.

The demand for high speed Field Programmable Gate Arrays (FPGAs) has always been on a rise. This was never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 10-220 MHz using CMOS. The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5 GHz were reported by B. S. Goda and Channakeshav et al. using SiGe 5HP technology. Using IBM's new 7HP technology, SiGe HBT devices with cutoff frequencies (f/sub T/) over 100 GHz can be fabricated. Apart from the improvement in device speed, architectural changes have been made to improve the speed and reduce the power. This paper is mainly going to elaborate on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGA. The entire Configurable Logic Block (CLB) has been implemented using 3 Current Mode Logic (CML) trees. The power consumption of the redesigned CLB is "5.04 mW - sequential, 3.36 mW - combinational" and the maximum operating frequency of the new logic cell is 11.7 GHz. Apart from these, 2 memory planes have been added to change the personality of the FPGA dynamically. The original Widlar current mirror has been replaced by a CMOS current mirror which avoids the loading effect.

A high speed, low power FPGA design is presented in this paper. This gigahertz FPGA design has an improved XC6200 structure. Redundant multiplexers are eliminated from critical signal path to enhance the performance of the previous design. By balancing between the power consumption and performance, the simulated clock rate is from 5 GHz to 20 GHz and the power consumption is from 4 mW to 12 mW per single cell in the IBM 7HP SiGe HBT BiCMOS process.

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuit's performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing.

The low operating speed of current CMOS Field Programmable Gate Arrays (FPGAs), i.e., 10-220 MHz, has prevented their use in high-speed digital applications. With the advent of IBM Silicon Germanium (SiGe) 7HP technology, designers have been able to design FPGAs operating in the gigahertz range. This paper is going to elaborate on the implementation of a 4-bit ripple-carry full adder (FA) on the new SiGe FPGA with new architectures and a novel power management strategy. The 1-bit FA can be realized in three Configurable Logic Blocks (CLBs). Apart from these, the FA can operate in multiple modes: FAST, NON-CRITICAL, SLOW and OFF. The propagation delays of the 1-bit FA and 4-bit ripple-carry FA are 240 ps and 675 ps respectively in the FAST mode. All the simulation and layouts were done using Cadence 4.4.6 and IBM SiGe 7HP design kit version 1.1.1.0.

This paper presents an improved Xilinx XC6200 FPGA using IBM SiGe BiCMOS technology. The basic cell performance is greatly enhanced by eliminating redundant signal multiplexing procedures. The simulated combinational logic result has a 30% shorter gate delay than the previous design. By adjusting and properly shutting down the CML current, this design can be used in lower-power consumption circuits. The total saved power is 50% of the first SiGe FPGA developed in the same group. Lastly, the FPGA with a 3-D stacked memory concept is described to further reduce the influence of parasitics generated by the memory banks. The circuit area is also reduced to make dense integrated circuits possible.

Field Programmable Gate Arrays (FPGAs) have always been used for applications like signal processing, rapid prototyping etc. With the advent of SiGe HBT devices, FPGAs have found new applications in high-speed digital-system design. Since SiGe HBTs can be used along with CMOS, it has made SiGe devices very popular. This paper elaborates new ideas in designing high-speed SiGe BiCMOS FPGAs. The architecture is based on Xilinx 6200. The paper explains new methods to cut down the number of trees in the circuit. Selective tree shutdown has been used to reduce power consumption. A new decoding logic has been developed where the address and data lines are shared. These ideas have improved the performance of SiGe FPGAs. The operating frequencies of the new Configuration Logic Block (CLB) is in the range of 1-20 GHz.

Implementation of a silicon germanium (SiGe) field programmable gate array (FPGA) has been described. The reconfigurable basic cell (BC) that evolved from the Xilinx XC6200 has been redesigned to achieve high speed with lower power consumption. The propagation delay of the BC in comparison to the BC implemented in the earlier generation SiGe process has been reduced to 18% of its original value (from 240 to 42 ps) and the power consumption has been comparably reduced. The range of power reduction is from 13% of its original value when the BC is fully turned on down to 2% when the power saving scheme is applied. A 20times20 SiGe FPGA with physical dimensions of 4.5times4.8 mm has been fabricated using the IBM 120 GHz (7HP) process. To deliver a 10 GHz clock, an H tree has been designed and implemented with reduced skew. To demonstrate its performance, a 4:1 multiplexer (MUX) has been mapped for comparison with various CMOS FPGAs. The SiGe FPGA can achieve an 8 Gbps transmission rate, which is a 40 times improvement over the same implementation on a Xilinx Virtex CMOS FPGA. Other comparisons between the SiGe FPGA and commercial FPGAs have also been included. From simulations and measurements, the SiGe FPGAs have been shown to have high performance that can successfully tackle gigahertz applications