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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed design of hybrid CLA based 32-bit CSA has been compared with conventional static CMOS based 32-bit CSA and 32-bit Ripple Cary Adder (RCA) by conducting simulation using Cadence Virtuoso. Power consumption and delay in the proposed 32-bit CSA found 322.6 (uW) and 0.556 (ns) whereas power and delay in the conventional 32-bit CSA was 455.4 (uW) and 0.667 (ns) respectively. We have done all the simulation using Cadence Virtuoso 90 nm tool.

This paper presents a method towards the improved performance parameters of conventional CMOS based 4-bit carry look-ahead adder. Conventional CLA adder has high numbers of transistors and high input impedance due to which various performance aspects are affected. Due to high input impedance, its delay and power consumption are high. Therefore, to increase the performance and to reduce delay, we have proposed an advanced version of CLA adder where hybrid logic based XOR gate and GDI AND gates have been used as input to reduce the transistor count as well as to improve performance. Finally, performance of modified adder has been compared with the conventional CLA adder. We have noticed that modified CLA adder showed better performance than the conventional CLA adder. Simulation has been done with Cadence virtuoso 90nm technology.

This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) logic. To test performance parameters, simulation has been conducted using Cadence Virtuoso in 65 nm technology. Moreover, a comparative analysis of the proposed design with 13 existing state of art FAs has been presented in this research to observe the performance improvements obtained by the proposed FA. In addition, the proposed and existing FAs have been cascaded to implement 4-bit, 8-bit, 16-bit and 32-bit adder to test their performance and feasibility in large structures. The proposed design exhibited remarkable performance both as single cell and cascaded mode. Besides, the proposed technique for FA design removes the defect of voltage degradation in GDI technique and low drivability of TG based design by utilizing C-CMOS logic in the output terminals.

A 4-bit Carry Look-Ahead (CLA) architecture for carry-generation process is proposed. CLA architecture proposed in this work uses complex CLA circuits for carry-generation rather than using carry-generate and carry-propagate functions which are used in the conventional process of 4-bit CLA architecture. Performance of the proposed CLA architecture is validated by performing simulation utilizing Cadence tools in standard 45 ​nm CMOS process. In order to prove effectiveness, performance of the proposed 4-bit CLA design is compared with existing 4-bit CLA designs. Moreover, as a possible application of the proposed design and to inspect performance in wide word length adder structure, the 4-bit CLA architectures (proposed and existing) are extended to 16-bits using Carry-Select Adder (CSA) architecture. Both as 4-bit cell and extended 16-bit structure, the proposed 4-bit CLA shows remarkable improvement in speed while maintaining quite acceptable level of power consumption. As a result, the proposed 4-bit CLA can be utilized as a highly suitable substitution of the existing 4-bit CLA architectures in high-speed microprocessor design.