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Sparc64 XIfx, the latest high-performance computing processor, includes a 34-core processor and achieves 1.1 teraflops of peak performance. This chip is designed for massive parallel supercomputer systems that realize high performance for a wide range of real applications. As groundwork for exascale supercomputing, it has made major technological changes from the previous Sparc64 processor in the instruction set architecture, microarchitecture, memory modules, and embedded interconnect.

Fujitsu's Sparc64 X is a processor for Unix servers that runs at a speed of 3 GHz and consists of 16 cores, a 24-Mbyte shared level-2 (L2) cache, memory controllers, I/O controllers, and system controllers for connecting multiple chips. The authors of this article enhanced the microarchitecture and introduced an extended instruction set called High-Performance Computing Arithmetic Computational Extensions (HPC-ACE), used previously in the K computer. The peak memory bandwidth is 102 Gbytes per second. These features realize extremely high-throughput performance. In addition, the authors added new functions to the processor core pipelines, which accelerate certain software tasks such as cryptographic processing. They call these functions "software on chip" (SWoC). Furthermore, they employ high-reliability technology used in mainframes to ensure stable operation of mission-critical systems. This article describes the past and current direction of the microarchitecture of the Sparc64 processor series, gives an overview of Sparc64 X, and presents results of testing the performance and power efficiency of SWoC.

The Sparc64 VIIIfx eight-core processor, developed for use in petascale computing systems, runs at speeds of up to 2 GHz and achieves a peak performance of 128 gigaflops while consuming as little as 58 watts of power. Sparc64 VIIIfx realizes a six-fold improvement in performance per watt over previous generation Sparc64 processors.