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Sorting is one of the most fundamental topics in computer science. Since partial sorting with lower costs would be much more feasible than the complete sorting method for some applications, this paper focuses on the architecture sorting N values from M inputs. To meet the real-time processing requirement, hardware acceleration is commonly employed to enhance the performance. However, high-speed computation usually raises power consumption drastically.To overcome that problem, a low-power, high-throughput, and modular hardware design of partial sorting network is presented. By applying a pointer-like design, the comparing modules move the indexes of samples instead of moving the input data directly. Power dissipation is reduced by minimizing switching activities and signal transitions. To prevent unnecessary comparing of the large data set, an iterative architecture is proposed which uses both the low-power sorting module and a novel clipping mechanism. The proposed design was simulated with a 90-nm cell library and the results are compared to those of other works on hardware sorting. Experiment results show that power consumption is reduced by 64.9 percent and high-throughput performance can also be achieved. [ABSTRACT FROM AUTHOR]

Hilbert–Huang transform (HHT) is an effective method for analyzing nonlinear systems and nonstationary signals. Empirical mode decomposition (EMD) is the core of HHT. In this paper, a flexible, low cost, and high-performance silicon intellectual property (SIP) core for the EMD is proposed to meet the high-speed requirements of various EMD applications. Variables in the proposed EMD SIP are parameterized as much as possible. Using the proposed auxiliary software system, the EMD SIP generator, users can choose various precisions, data lengths, extrema extraction methods, envelope generation methods, stopping criterion methods, and computation units for different EMD applications. All circuits generated using the proposed EMD SIP generator can be operated at 200 MHz using the 90-nm cell library from the Taiwan Semiconductor Manufacturing Company (TSMC), and they can be easily used for various applications and hardware architectures. [ABSTRACT FROM PUBLISHER]

Image scaling is an important technique that is widely used in many image processing applications. This paper presents a novel scaling algorithm for the implementation of 2-D image scalar. The proposed interpolation method is based on the interpolation error theorem often mentioned in numerical analysis. A bilateral error-amender is used to make the interpolation more precise, and an edge-weighted scheme enhances the edge features of the scaled images. Extensive experimental results demonstrate that the proposed method can obtain better performance than previous methods in both quantitative evaluation and visual quality. This paper also presents an efficient very large-scale integrated architecture for the proposed method. The cooperation and hardware sharing techniques greatly reduce hardware cost requirements. Using a nine-stage pipeline, the proposed scaling circuit contains 13 k gate counts and yields a processing rate of approximately 278 MHz using TSMC 0.13-\mum technology. The hardware cost of the proposed circuit is low, making it a good candidate for high-quality image scaling applications. [ABSTRACT FROM PUBLISHER]

Defogging is an essential preprocessing technique for object detection in computer vision-based systems and has been widely used in outdoor surveillance system applications. This paper proposes an efficient defogging algorithm for both static images and videos. Considering real-time applications, the proposed defogging algorithm involves a low-cost hardware oriented design that is based on an atmospheric scattering model and dark channel prior. Compared with previous low-complexity techniques, simulation results indicated that the proposed design demonstrated superior performance in terms of quantitative and qualitative evaluations. A weighting technique and a contour preserving estimation approach are adopted alternately to refine the factors in the defogging process. Furthermore, in the atmospheric light estimation, an adjuster is applied to the video for preventing “flicker” which means that the brightness changes dramatically between two neighbor frames in the video. Hence, the proposed algorithm is suitable for video defogging applications, which have not been dealt with in previous approaches. To achieve the requirement of real-time applications for both static and dynamic images, an implementation of seven-stage very-large-scale integration architecture for the proposed algorithm is presented. By using TSMC 0.13- $\mu {\mathrm{ m}}$ technology, the design yielded a processing rate of approximately 200 Mpixels/s. [ABSTRACT FROM AUTHOR]

Color filter array interpolation, also known as demosaicking and “debayering,” is a crucial process for image reconstruction in digital still cameras. This paper presents an edge-oriented demosaicking method and an efficient very-large-scale integration (VLSI) architecture for color interpolation. The design uses simple operations (addition, subtraction, shift, and comparator) and nearest neighboring pixels to catch the color difference and edges. The required line buffering of the proposed design is four lines; therefore, its hardware cost is low. Our extensive experiments revealed that the proposed technique preserved edge features and exhibited excellent quantitative evaluation and visual quality performances. Compared with the previous VLSI implementations, the proposed design achieved superior image qualities. The synthesis results revealed that by using Taiwan Semiconductor Manufacturing Company 0.18- $\mu \text{m}$ technology, the proposed design yields a processing rate of approximately 200M samples per second. [ABSTRACT FROM AUTHOR]

In this letter, a fast and efficient haze removal method is presented. We employ an extremum approximate method to extract the atmospheric light and propose a contour preserving estimation to obtain the transmission by using edge-preserving and mean filters alternately. Our method can efficiently avoid the halo artifact generated in the recovered image. To meet the requirement of real-time applications, an 11-stage pipelined hardware architecture for our haze removal method is presented. It can achieve 200 MHz with 12.8 K gate counts by using TSMC 0.13-\mum technology. Simulation results indicate that our design can obtain comparable results with the least execution time compared to previous algorithms and is suitable for low-cost high-performance hardware implementation for haze removal. [ABSTRACT FROM PUBLISHER]