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With continuous improvement and update of embedded Linux kernel, embedded technology has been widely used in handheld devices and industrial control field. Therefore, a user-friendly graphical user interface (GUI) is essential for these applications. This paper firstly presents the design method for transplanting Qt on embedded platform of ARM9. Secondly it elaborates the device driver development and Qt interface development in Linux system with a Qt test program. All transplantation method of Qt and test program have been tested and verified on the ARM9 platform.

In this paper, 0.05 grade three-phase main control system of multi-station meter testing equipment (MTE) is presented. This design is based on the S3C2440 core board as the control core, and the software is based on Windows CE(WINCE) embedded operating system. The device is displayed and controlled by 7-inch Touch Screen. The main control system communicate with the error instrument and PC through Controller Area Network (CAN) bus, and the largest number of error instruments can connect to CAN bus is 100. The main control system communicates through RS232 bus with three-phase signal source and standard electric energy meter, through RS485 bus with programmable power amplifier. In this device, calibration of energy meters can not only through the PC software, but also use the main control system. Compared to the traditional design of the electric energy meter calibration device, the design’s the man-machine interface is more optimized, the number of electric energy meters can be test in the same time is more, faster communication, stronger anti-interference ability, and calibration is more efficiency.

This paper analyzes the negative influence of dead-time,point out the shortcomings of traditional dead-time compensation methods , and then present a dead-time compensation method. Simulink simulation shows that the proposed method is effective. The proposed method is applied to a 15kW inverter which is controlled by STM32F103 MCU,and it can significantly reduce the THD value of the inverter output voltage waveform. The experiment proved that this method is simple and reliable, with good results.

In order to improve the step accuracy of two-phase hybrid stepping motors, this paper presents a high-performance stepping motor driver based on controllable dead-time compensation. After CPLD(Complex Programmable Logic Device) logical processing, the subdivision drive signal created by microcontroller STM32 becomes a complementary dead-time compensation drive signal which can realize precise control of stepper motor. The experiment shows that this program not only has effectively reduced the power consumption of the stepping motor, but also made whole system cost less.

We have designed a photoelectric yarn signal acquisition system, which is based on the STM32 processor, having a sample rate up to 270kHz, and uploading data collection through synchronous parallel communication mode; Owing to the large noise of yarn signal and the unobviousness of yarn defect, we respectively adopting wiener filter and mean filter to filter this signal; The simulation result of matlab has manifested that both the wiener filter and mean filter can effectively decrease the noise level of the yarn signal and make the nep defects easier to identify, and that the wiener filter applies to application where the yarn speed is higher , while the mean filter is appropriate to the lower speed spinner.

In this paper, the application of a FPGA-based large-screen and high-resolution display accelerator technology in full-automatic textile machinery (computerized flat knitting machine) is studied. The design of traditional computerized knitting machine system is difficult to support the display of large screen and high resolution operating interface. Therefore, a displaying accelerator is designed in this paper. It comprises of FPGA, configuration chip, SDRAM and LVDS transmitter chip, is located between the embedded main processor and high resolution TFT LCD screen of computerized flat knitting machine, and implements the modules such as display acceleration logic and SDRAM controller relying on Verilog HDL programming in FPGA. The computerized flat knitting machine, applying displaying acceleration technology, can present its dynamic color interface on an 800 x 600 resolution TFT LCD (10.4") on the condition that real time, reliability and cost can be ensured.

In this paper, the application of a FPGA-based large-screen and high-resolution display accelerator technology in full-automatic textile machinery (computerized flat knitting machine) is studied. The design of traditional computerized knitting machine system is difficult to support the display of large screen and high resolution operating interface. Therefore, a displaying accelerator is designed in this paper. It comprises of FPGA, configuration chip, SDRAM and LVDS transmitter chip, is located between the embedded main processor and high resolution TFT LCD screen of computerized flat knitting machine, and implements the modules such as display acceleration logic and SDRAM controller relying on Verilog HDL programming in FPGA. The computerized flat knitting machine, applying displaying acceleration technology, can present its dynamic color interface on an 800 x 600 resolution TFT LCD (10.4") on the condition that real time, reliability and cost can be ensured.