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In this article, we introduce an automatic stream computing reoptimization flow from ASICs to field-programmable gate arrays (FPGAs). Complex VLSI designs need to be prototyped and/or emulated on FPGAs. The main problem that we address in this article is that configurations optimized when targeting ASICs are often, as we will show in this article, highly un-optimal when remapped onto an FPGA. Thus, this article proposes a method to first generate a variety of dataflow configurations targeting an ASIC given multiple behavioral descriptions for high-level synthesis (HLS) and then, based on a compositional predictive model, automatically reoptimize the dataflow when mapped onto an FPGA. The experimental results show that our proposed method works well and that it is very fast. [ABSTRACT FROM AUTHOR]

This paper studies the acceleration of numerical simulations executed on Field-Programmable Gate Arrays (FPGAs) for electric machines presented by voltage-behind-reactance (VBR) models. In VBR models, the stator dynamics are modeled in abc coordinates, while the rotor dynamics are formulated in qd reference frame. Both induction motors and synchronous generators, operating without and with magnetic saturation, are considered. Once VBR models of these machine types are reviewed, their dynamic models are discretized using Runge-Kutta numerical routines. The detailed mapping of such discrete models to FPGA is provided using High-Level Synthesis, which directly converts untimed descriptions into VHDL or Verilog. An automated method finds the fastest FPGA architecture by finding the best set of synthesis options. Experimental results show that our FPGA-based acceleration flow leads to about 92-168 times average simulation speed-up for various machine types compared to the MATLAB simulation. [ABSTRACT FROM AUTHOR]