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The effects of the parasitic gate capacitance and gate resistance (Rg) on the radiofrequency (RF) performance are investigated in LG = 0.15 μm GaN high‐electron‐mobility transistors with T‐gate head size ranging from 0.83 to 1.08 μm. When the device characteristics are compared, the difference in DC characteristics is negligible. The RF performance in terms of the current‐gain cut‐off frequency (fT) and maximum oscillation frequency (fmax) substantially depend on the T‐gate head size. For clarifying the T‐gate head size dependence, small‐signal modeling is conducted to extract the parasitic gate capacitance and Rg. When the T‐gate head size is reduced from 1.08 to 0.83 μm, Rg increases by 82%, while fT and fmax improve by 27% and 26%, respectively, because the parasitic gate–source and gate–drain capacitances reduce by 19% and 43%, respectively. Therefore, minimizing the parasitic gate capacitance is more effective that reducing Rg in our transistor design and fabrication, leading to improved RF performance when reducing the T‐gate head size. [ABSTRACT FROM AUTHOR]

The effects of the parasitic gate capacitance and gate resistance (Rg) on the radiofrequency (RF) performance are investigated in LG = 0.15 μm GaN high-electron-mobility transistors with T-gate head size ranging from 0.83 to 1.08 μm. When the device characteristics are compared, the difference in DC characteristics is negligible. The RF performance in terms of the current-gain cut-off frequency (fT) and maximum oscillation frequency (fmax) sub-stantially depend on the T-gate head size. For clarifying the T-gate head size dependence, small-signal modeling is conducted to extract the parasitic gate capacitance and Rg. When the T-gate head size is reduced from 1.08 to 0.83 μm, Rg increases by 82%, while fT and fmax improve by 27% and 26%, respectively, because the parasitic gate–source and gate–drain capacitances reduce by 19% and 43%, respectively. Therefore, minimizing the parasitic gate capacitance is more effective that reducing Rg in our transistor design and fabrication, leading to improved RF performance when reducing the T-gate head size.

The effects of fringing capacitances on the high-frequency performance of T-gate GaN high-electron mobility transistors (HEMTs) are investigated. Delay time components have been analyzed for gate-recessed InAlN/GaN HEMTs with a total gate length of 40 nm and fT/f\max of 225/250 GHz. It is found that the gate extrinsic capacitance contributes significantly to the parasitic delay—approximately 50% of the total delay in these highly scaled devices. The gate extrinsic capacitance comprises two components: 1) parallel plate capacitances between the T-gate and the surrounding electrodes and 2) the fringing capacitance between the gate stem and the access regions. Detailed study of the gate electrostatics reveals that the later, the fringing capacitance between the T-gate stem and the device access region, ultimately determines the lower limit of the extrinsic capacitance Cext; this minimum Cext can be realized experimentally using a large gate stem height (>200~nm) and employing low-k passivation dielectric. Since the corresponding parasitic delay can be expressed as Cext/gm,{\rm int}, this paper also highlights the importance of maximizing gm,int in ultrascaled HEMTs by adopting strategies to enhance carrier velocity. [ABSTRACT FROM AUTHOR]