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Vertical power devices require significant attention to their edge termination designs to obtain higher breakdown voltages without substantial increase in ON-state resistance. A simple edge termination structure for a GaN p-n diode is proposed, comprising a full layer lightly doped p-type GaN region underneath the higher doped ${p} +\!+$ contact layer. A TCAD model of the device is developed, and removal of the portions of ${p}$ ++ cap outside of the device active area in simulations is shown to increase the device blocking voltage capability. It causes the depletion width to increase in the lightly doped p-type layer and allows it to act similar to a junction termination extension (JTE). These predictions are validated empirically, resulting in a 52% measured increase in breakdown capability after selective removal of the ${p}$ ++ cap. This simple edge termination technique can be formed with only a single low-energy nitrogen implant or etching procedure, greatly increasing its manufacturability over more complex structures. Design optimization studies are pursued in TCAD to determine optimal parameter values for further improving breakdown performance. It is shown that the proposed edge termination technique can be employed to produce future high voltage vertical GaN devices without a significant gain in ON-state resistance and with wide tolerance to process variations. [ABSTRACT FROM AUTHOR]

Present GaN technology consists primarily of heteroepitaxial, lateral high electron mobility transistors; however, high-power devices would be much more efficiently manufactured with a vertical geometry due to better blocking voltage scaling. This technology has yet to be realized due to the inconsistency of GaN wafer properties. These inconsistencies can be detected with several long-range, non-destructive techniques including Raman spectroscopy, optical profilometry, and photoluminescence mapping. In particular, Raman spectroscopy is an effective tool for determining the carrier concentration of GaN substrates and whether the wafers are uniform or inhomogeneous. In this work, vertical p-i-n GaN diodes are fabricated using both uniform and inhomogeneous wafers determined by using the A1 Raman peak position to monitor carrier concentration. The inhomogeneous samples have regular patterns of varying conductivity as a result of electron-donating defects brought about by changes in crystal stress. By avoiding these defects, we have found that diode performance improves by increasing the +/− 10 V rectification ratio by up to a factor of 5X and reducing the 200 V reverse bias leakage current by several orders of magnitude. Using the higher quality substrates with uniform electron carrier concentrations can improve the rectification ratio by another order of magnitude. [ABSTRACT FROM AUTHOR]

GaN is a favorable martial for future efficient high voltage power switches. GaN has not dominated the power electronics market due to immature substrate, homoepitaxial growth, and immature processing technology. Understanding the impact of the substrate and homoepitaxial growth on the device performance is crucial for boosting the performance of GaN. In this work, we studied vertical GaN PiN diodes that were fabricated on non-homogenous Hydride Vapor Phase Epitaxy (HVPE) substrates from two different vendors. We show that defects which stemmed from growth techniques manifest themselves as leakage hubs. Different non-homogenous substrates showed different distribution of those defects spatially with the lesser quality substrates clustering those defects in clusters that causes pre-mature breakdown. Energetically these defects are mostly mid-gap around 1.8Ev with light emission spans from 450nm to 700nm. Photon emission spectrometry and hyperspectral electroluminescence were used to locate these defects spatially and energetically. [ABSTRACT FROM AUTHOR]

Plasma etching of p-type GaN creates n-type nitrogen vacancy (VN) defects at the etched surface, which can be detrimental to device performance. In mesa isolated diodes, etch damage on the sidewalls degrades the ideality factor and leakage current. A treatment was developed to recover both the ideality factor and leakage current, which uses UV/O3 treatment to oxidize the damaged layers followed by HF etching to remove them. The temperature dependent I–V measurement shows that the reverse leakage transport mechanism is dominated by Poole–Frenkel emission at room temperature through the etch-induced VN defect. Depth resolved cathodoluminescence confirms that the damage is limited to first several nanometers and is consistent with the VN defect. [ABSTRACT FROM AUTHOR]

We report selective area n-type doping using ion implantation of Si into semi-insulating, C-doped GaN samples activated using both conventional rapid thermal annealing (RTA) and 30 atm N2 overpressure annealing. Implanted regions were tested for Si activation using Circular Transmission Line Measurements (CTLM), while linear and circular photoconductive switches (PCSS) in the unimplanted regions were used as a test vehicle to separate implanted Si dopant activation from leakage paths generated by N vacancy formation due to damage and decomposition during annealing. We observed that at an optimal temperature around 1060 °C, a low contact resistivity of $1\times 10^{-6}\,\,\Omega $ -cm2 was obtained while preserving the breakdown of the unimplanted regions. [ABSTRACT FROM AUTHOR]