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8 results on '"Tamukoh, Hakaru"'

1. Design and Implementation of Pulse-Coupled Phase Oscillators on a Field-Programmable Gate Array for Reservoir Computing

Author

Pramanta, Dinda, Tamukoh, Hakaru, Filipe, Joaquim, Editorial Board Member, Ghosh, Ashish, Editorial Board Member, Prates, Raquel Oliveira, Editorial Board Member, Zhou, Lizhu, Editorial Board Member, Yang, Haiqin, editor, Pasupa, Kitsuchart, editor, Leung, Andrew Chi-Sing, editor, Kwok, James T., editor, Chan, Jonathan H., editor, and King, Irwin, editor

Published
2020
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2. Impact of PS load on FPGA object detection system performance

Author

Watanabe, Yusuke and Tamukoh, Hakaru

Subjects
PL, Parallel Processing, Zynq, System Performance, PS, FPGA
Abstract

A field-programmable gate array (FPGA) device which has a Zynq architecture becomes popular these days. It is featured by integration of processing system (PS) and programmable logic (PL) into a single chip. While we tend to focus on the performance of PL, we can not ignore PS load completely. In this paper, using a Zynq FPGA board, we explore how our object detection system performance changes with PS load and report our experiment results., The 2023 International Conference on Artificial Life and Robotics (ICAROB 2023), February 9-12, 2023, on line, Oita, Japan

Published
2023

3. Restricted Boltzmann Machines Without Random Number Generators for Efficient Digital Hardware Implementation

Author

Hori, Sansei, Morie, Takashi, Tamukoh, Hakaru, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Villa, Alessandro E.P., editor, Masulli, Paolo, editor, and Pons Rivero, Antonio Javier, editor

Published
2016
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4. FPGA Implementation of Autoencoders Having Shared Synapse Architecture

Author

Suzuki, Akihiro, Morie, Takashi, Tamukoh, Hakaru, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Hirose, Akira, editor, Ozawa, Seiichi, editor, Doya, Kenji, editor, Ikeda, Kazushi, editor, Lee, Minho, editor, and Liu, Derong, editor

Published
2016
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5. Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing

Author

Suedomi, Yasuhiro, Tamukoh, Hakaru, Tanaka, Michio, Matsuzaka, Kenji, Morie, Takashi, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Lee, Minho, editor, Hirose, Akira, editor, Hou, Zeng-Guang, editor, and Kil, Rhee Man, editor

Published
2013
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6. A Dynamically Reconfigurable Platform for Self-Organizing Neural Network Hardware

Author

Tamukoh, Hakaru, Sekine, Masatoshi, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Wong, Kok Wai, editor, Mendis, B. Sumudu U., editor, and Bouzerdoum, Abdesselam, editor

Published
2010
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7. Parameterized digital hardware design of pulse-coupled phase oscillator networks.

Author

Suedomi, Yasuhiro, Tamukoh, Hakaru, Matsuzaka, Kenji, Tanaka, Michio, and Morie, Takashi

Subjects
*COMPUTER input-output equipment, *PHASE oscillations, *SYNCHRONIZATION, *DISCRETIZATION methods, *ELECTRIC circuits
Abstract

This paper proposes a parameterized digital hardware design of pulse-coupled phase oscillator networks that exhibit various synchronization phenomena. We introduce a discretization model with three-valued coupled functions to construct simplified pulse-coupled phase oscillators for parameterized design. The designed digital phase oscillator circuit can change the calculation accuracy and the coupling function shape of oscillators by parameters. One- and two-dimensional pulse-coupled phase oscillator networks are emulated using the designed phase oscillators by setting parameters for the desired network. Experimental results show that the proposed circuit emulates in-/anti-phase and different (out-of-phase) synchronization in two pulse-coupled phase oscillators effectively in an analog large scale integration implementation, and also various synchronization phenomena are observed in large-scale one- and two-dimensional networks. [ABSTRACT FROM AUTHOR]

Published
2015
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8. 2D/3D FPGA array for brain process and numerical computation.

Author

Li, Jiang, Takahashi, Kenichi, Tamukoh, Hakaru, and Sekine, Masatoshi

Abstract

We propose an FPGA Array structure that is designed to the scalable structure for executing brain processes and numerical computation for 3-D problem, and the circuits in FPGA Array are controlled from the application program running in host PC directly. Many circuits for brain processes are designed to evaluate the 3-D FPGA, also we implement arithmetic circuits that calculate 2D Poisson equation by the finite difference method to shows numerical computation performance. We also show the results of circuits for the brain processes such as voice recognition, voice synthesis, and image recognition with Self Organizing Map. We estimate the gate count of the circuit for practical brain processes. [ABSTRACT FROM PUBLISHER]

Published
2012
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