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Motion detection has various applications in machine vision fields, UAVs and robotics. Real-time motion detection requires fast computation of the optical flow. For this purpose, seems that FPGA is an appropriate platform for implementation of the optical flow algorithms. In this paper, a high performance FPGA based realization for the Horn and Schunck optical flow algorithm is proposed. The proposed implementation is a fast solution for the iterative Horn and Schunck optical flow algorithm. The proposed implementation uses parallel storage units which facilitates memory access and computations in a single clock. The designed hardware requires only one clock for the execution of the major operations on a motion vector computation. Applying parallel storages is an innovative approach for improving performances of the designed implementation. Using the proposed method significantly reduces consumed clocks and improves the efficiency of the implemented algorithm. The Cyclone II FPGA is utilized as implementation platform for this work. Using proposed method the optical flow calculated between two successive 240*320 pixels frames and the motion vectors are achieved. The resultant output throughput is 734.3 Kpixel/s which is appropriate for real-time motion detection. [ABSTRACT FROM PUBLISHER]