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Track-and-hold (T&H) circuits are used in a variety of applications. Noise is a key parameter in a T&H and can be traded for settling time or power consumption. The classical T&H noise design methodology considers only white noise sources, neglecting low-frequency noise sources. Although low-frequency noise contributions have been analyzed in the literature, an insightful, design-oriented analysis for flicker noise that can also be extended for arbitrary noise sources has not been proposed yet. In this brief, we present a time-domain noise analysis for a charge-redistribution T&H circuit. The analysis considers the noise contribution from white and 1/f sources. A design-oriented expression to compute the excess noise power due to flicker noise, as a function of the sampling rate, the intended T&H resolution, and the noise parameters, is obtained. This expression shows the dependence of the relative contribution of flicker noise over white noise, on the T&H design parameters. A simplified expression allows one to assess the relative contribution of flicker noise during an early stage of the design flow.

This paper presents a detailed investigation of audible noise characterization of filter capacitors by investigating the noise radiation characteristics and analyzing the effect of voltage frequency, phase angle, and magnitude on a single capacitor unit. First, the noise radiation for capacitor surfaces was characterized theoretically using finite rectangular plate model and experimentally measured in a semianechoic room. Second, voltage frequency impact on the noise distribution was investigated through simulation. The simulation results show that noise directivity increases with increasing frequency. The excitation frequency impact on the radiation ratio and the noise level was characterized through a sweep-frequency experiment. Our investigations show that the noise frequency response below 500 Hz is quite low, while from 500 to 2000 Hz, it is significant and increases slowly. Third, the impact of the voltage phase angle on the noise level was investigated. The results show a noise-level difference of 3.9 dB for different phase angles. Finally, we present the voltage magnitude impact on the noise level. Our theoretical analysis and experimental study show a linear relationship between the sound power level and the logarithm of the voltage magnitude with a slope of 40.

A novel technique for reducing phase noise of LC cross coupled oscillators is proposed, using second harmonic filtering of the tail current noise. Using a LC network in between tail current and switching transistors, second harmonic of the tail current noise is filtered out. The filtering circuit works simultaneously as low pass and band stop filters. Therefore, output phase noise is reduced. Three circuits including basic cross coupled oscillator with tail current, and two cross coupled oscillators with conventional and proposed method of tail current noise second harmonic filtering are designed and simulated in 0.13m CMOS technology, with the same power consumption from 1.2V supply. Simulation results show that for the proposed circuit, at 2GHz frequency and 1MHz offset, phase noise and Figure of Merit (FoM) are 130dBc/Hz and 192.3dB, respectively. Compared to basic and conventional circuits, proposed method presents phase noise improvements of 13dB and 7.5dB, respectively, at the cost of increased die area, due to the filtering inductor. Display Omitted

Voltage noise measurements on close to optimally doped YBa2Cu3O7-δ nanostructures have been performed. The measured resistance noise at temperature T = 96 K (above critical temperature $T_{C}$ = 85 K) shows a quadratic dependence on the bias current, e.g., the voltage power spectral density $S_{V}\alpha$ V 2. Moreover, the normalized voltage noise $S_{V}$ / V 2 is inversely proportional to the device volume. This is a clear indication that the noise is the result of an ensemble of independent resistive fluctuators, evenly distributed within the sample volume. For our structures, we obtain a product $S_{V}$ / V 2 × Vol . = const . a 6 × 10−33 m3/Hz resulting in a Hooge's parameter 3.4 × 10−4, which is among the lowest reported in literature. At lower temperature, T = 2 K (well below $T_{C}$ ) the total voltage fluctuations are given by the combined effect of critical current fluctuations and resistance fluctuations. For the critical current noise, we obtain a product $S_{I}/I_{C}$ 2 × Vol . = const . a 6 × 10−32 m3 /Hz. The larger value of the relative critical current noise is most probably due to the fact that the critical current is determined by edge effects whereas the resistance is given by the total volume of the device.

The possibility of determination of the number of localized capture centers of defects (relaxators) that cause low-frequency noise in a particular frequency range has been investigated. Here it is shown that a minimum number of relaxators is needed to generate 1/f type low-frequency noise only when relaxation times are arbitrarily distributed one-by-one in every two-octave range. The expression for estimation of the low-frequency noise level of the sample under test is presented. The presented expression for 1/f noise explains not only the noise level dependence both on the frequency and number of defects in the sample but also the observed noise intensity dependence on the mobility of free charge carriers. It is shown that the main source that causes low-frequency noise in homogeneous semiconductors is the charge carrier capture–emission process.

To explain the current dependences of the mean-square value of low-frequency (LF) noise current in green InGaN light emitting diodes (LEDs), a double stage low-frequency noise equivalent circuit of the LED is proposed. It is shown that the nonmonotonic dependence of the LF noise on the injection current in the LED can be explained by the effect of two LF noise generators: a noise current generator, which is localized near the heterojunction and is determined by tunnel-recombination processes at the interface, and a generator determined by recombination processes in the active region of the structure.

In part I, we extensively analyzed the results of the low-frequency noise characterization in advanced SiGe:C heterojunction bipolar transistors. In this paper, we demonstrate that base and collector noise spectral densities are partially correlated. The correlation is investigated by studying the coherence function at different bias conditions. The coherence reveals a frequency dependence at lower bias due to the presence of dominant generation–recombination mechanisms, whereas at higher bias, the coherence approaches unity. The bias dependence of the coherence is studied in several transistor geometries. In addition, a partially correlated base and collector 1/f noise model is proposed and implemented in HiCuM. Modeling results are in agreement with the measured data.

In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/ $f$ noise, generation–recombination (G–R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/ $f$ and G–R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/ $f$ noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation.

This paper analyzes different noise components in MEMS gyroscope silicon structure, including mechanical–thermal noise (MTN), electronic-thermal noise (ETN), flicker noise (FN) and Coriolis signal in-phase noise (IPN). The structure equivalent electronic model is established, and the improved differential interface is proposed based on weak signal detection technology, after that, the noise components in silicon structure are introduced and analyzed in sense open loop. The quadrature error (QE) signal automatically cancellation loop is proposed, and the results of the experiment indicate that the equivalent angular rates of QE and IPN are 46°/s and 4.55°/s respectively. The interfaces contrast experiments show that the DC noise and the useful signal amplitudes of differential and single-side detection interfaces are −49.8 dBmV, −16.8 dBmV and −39.8 dBmV (−42.1 dBmV), −22.1 dBmV (−22.2 dBmV), which confirms the differential interface has better SNR. The carrier experiments also illustrate that higher carrier frequency (from 500 kHz to 10 MHz) can restrain DC noise (from −19.8 dBmV to −54.2 dBmV) better, which demonstrate the FN is the dominant noise component of the silicon structure under normal temperature. The temperature experiments show the DC noise enhances from −48.5 dBmV to −14.6 dBmV over the range 20 °C to 60°C while the useful signal amplitude remains around -16.6dBmV, and this phenomenon indicates the MTN and ETN become the dominant structure noise components gradually with temperature rising.

Proposed method of calculation of flicker-noise power provided in published experimental results regarding investigation of flicker processes in real material of electronic devices. It is shown that during evaluation of signal/noise ratio in electronic devices in the range of low frequencies the flickernoise level should be taken 3–4 times bigger than the thermal noise level.

In this paper, an improved radio-frequency (RF) noise model is extended for silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) by applying RF avalanche delay mechanism to investigate noise performance in the breakdown region where reliability is a concern. The impact of inductive feedback due to base–collector (BC) junction avalanche breakdown on noise performance is analyzed and explained by utilizing this improved noise model incorporating an inductive network. The avalanche effects on noise sources are verified and explained physically by the dead-space theory. The contributions of electrons and holes to the avalanche noise are taken into account by including an electron- and hole-breakdown network in the presented noise model. The presented method is compared with the conventional approach. When the avalanche noise is absorbed by base and collector noise sources as in the conventional RF noise model without a breakdown network, simulated noise parameters deviate from experimental data at breakdown. Instead, good agreement between measured and simulated noise parameters and $S$ -parameters from the presented RF noise model is achieved in the inductive breakdown and active regions. The presented noise model and the obtained parameters can be applied to SiGe HBT circuits for reliability investigation.

Variation of low frequency noise including 1/f noise and Lorentzian spectra is the dominant source of variations for noise equivalent power (NEP) of THz detectors using a forward biased diode connected NMOS transistor. Elimination of the impact of low frequency noise variation to NEP with 1-V amplitude AC biasing at 44MHz is demonstrated in 830-GHz detectors using a diode connected PMOS transistor. It should be possible to apply this technique to eliminate the impact of low frequency noise variations in THz NMOS and Schottky diode detectors. Lastly, the low frequency noise voltage power spectral density of AC biased diode connected PMOS transistors is comparable to that of commercial GaAs detectors.

Made available in DSpace on 2018-12-11T17:25:01Z (GMT). No. of bitstreams: 0 Previous issue date: 2015-11-01 In this paper, the low-frequency (LF) noise in standard n-channel triple-gate Bulk FinFETs has been experimentally investigated with variation in the fin widths (WFin), channel lengths (L) and gate dielectric. The origin of the noise will be analyzed in order to understand the physical mechanisms involved in 3D device architectures. Although the device scaling brings the idea of noise reduction, we show the opposite behavior because already single electron trapping has a marked impact on the device operation. Significant variation in the noise spectral density has been observed, which is related to the random occurrence of excess Lorentzian components (1/f2-like), associated with generation-recombination (GR) noise. In addition, the gate-voltage-dependent GR noise peaks have been studied, which are assigned to gate oxide traps. UNESP - Univ Estadual Paulista, Group of Automation and Integrated Systems, Av. Três de Março, n. 511 LSI/PSI/USP, University of Sao Paulo, Av. Prof. Luciano Gualberto, trav. 3, n.158 Imec, Kapeldreef 75 E. E. Department, KU Leuven, Kasteelpark Arenberg 10 UNESP - Univ Estadual Paulista, Group of Automation and Integrated Systems, Av. Três de Março, n. 511

In this paper, we report the observation of random telegraph noise (RTN) in highly scaled InGaAs gate-all-around (GAA) MOSFETs fabricated by a top-down approach. RTN and low-frequency noise were systematically studied for devices with various gate dielectrics, channel lengths, and nanowire diameters. Mobility fluctuation is identified to be the source of 1/f noise. The 1/f noise was found to decrease as the channel length scaled down from 80 to 20 nm comparing with classical theory, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET. Low-frequency noise in ballistic transistors is discussed theoretically.

According to the discussion of noise sources and up-conversion mechanisms of flicker noise, an LC oscillator with improved self-switched biasing and decoupling capacitor is presented. To minimize the 1/f3 phase noise, both source noise and conversion gain of flicker noise are desirable to reduce, rather than only one way in previous works. Flicker noise from tail-biasing transistors is reduced by self-switched biasing technology, and the up-conversion of flicker noise from cross-coupled pair is suppressed by decoupling capacitor at the same time. Phase noise and key parameters influencing phase noise are analyzed in detail. To guide the design, simple way to get optimum values of key parameters is also presented. This oscillator can work at low supply voltage to reduce power consumption considerably compared to conventional self-switched biasing. The proposed oscillator is fabricated in 0.18 μm CMOS process, and exhibits a low phase noise of ?77.5 dBc/Hz (FoM = 181) and ?122.8 dBc/Hz (FoM = 186) at 10 kHz and 1 MHz offset, respectively, from oscillation frequency of 2.55 GHz while dissipating 2.7 mA with 1.2 V supply voltage.

An analysis of the flicker noise conversion to close-in phase noise in complementary metal-oxide semiconductor CMOS differential inductance-capacitance LC-voltage controlled oscillator is presented. The contribution of different mechanisms responsible for flicker noise to phase noise conversion is investigated from a theoretical point of view. Impulse sensitivity function theory is exploited to quantify flicker noise to phase noise conversion process from both tail and core transistors. The impact of different parasitic capacitances inside the active core on flicker noise to phase noise conversion is investigated. Also, it is shown how different flicker noise models for core metal-oxide semiconductor MOS transistors may result in different close-in phase noise behaviors. Based on the developed analysis, design guidelines for reducing the close-in phase noise are introduced. Copyright © 2015 John Wiley & Sons, Ltd.

This paper aims to investigate time-domain characteristics of the audible noise caused by single corona source under positive corona discharge. The obtained time-domain waveform of the audible noise consisted of a series of bipolar sound pressure pulses. After the background noise was successfully removed, the characteristics of audible noise pulses, such as amplitudes of each pulse, pulse rate and apparent duration time, were analyzed in this paper. Using the applied voltage and the onset voltage as variables, empirical formulas were derived from the measured results to predict the pulse rate and the amplitudes of the pulses. Furthermore, a typical waveform in the form of segmented double exponential function was developed to simulate the audible noise pulse. The rationality of the typical waveform was confirmed both in time domain and in frequency domain. Finally, some qualitative explanations for the generation of the bipolar pulse waveform of audible noise were given. Based on the remaining space charges characteristics, the influences of the applied voltage on the amplitude and pulse rate of the audible noise pulses were studied qualitatively.

Based on high output saturation power of quantum dot semiconductor optical amplifiers, it has been shown that exploiting a saturating holding beam (HB) can effectively suppress amplitude noise with HB power as a tunability degree of freedom. A simultaneous study of amplitude noise and pattern effect induced at high data rates on the quality factor of output signal reveals that desirable $Q$ -factor level can be obtained through modifying the bias current density and HB power. An upper data rate limit for $Q$ -factor penalty-free operation at various input signals to noise ratios is also predicted. A wide power range for the applied HB is promising for developing a tunable noise suppression scheme.

Landauer---Buttiker shot noise formula only considers the impact of Pauli exclusion principle on noise, but not the impact of Coulomb repulsion among carriers. A theory recently derived by the authors is able to include also the impact of Coulomb repulsion, and provides a computational methodology to obtain noise properties on a more complete physical basis. We review recent results from the application of this methodology with the use of in-house developed computational electronics tools. We show that in a one-dimensional FET, electrostatic repulsion among charge carriers in the channel can be responsible for strongly suppressed or enhanced shot noise with respect to the Poissonian Noise, or to the noise level provided by Landauer---Buttiker formula. This is very relevant for device and circuit design, since current semiconductor technology evolution has brought nanoscale FETs very close to the limit of one-dimensional FETs.

In this paper, analytical models for high-frequency drain-current noise, gate-current noise, and their cross-correlation of MOSFETs are presented with an emphasis on the weak- and moderate-inversion regions. Unified expressions offering excellent continuity and smoothness from weak- to moderate- and strong-inversion regimes were developed. It is demonstrated that the continuity and the accuracy of the calculated four noise parameters, such as minimum noise figure, normalized noise resistance, and optimum source conductance and susceptance, are significantly improved in the weak- and moderate-inversion regions by using the proposed unified noise model, which includes the junction-induced drain-current noise. A figure-of-merit is introduced to determine the optimum gate biasing point of MOSFETs, where high gain can be achieved at low driving power and low operating noise. The results obtained from the proposed model manifest good agreement with the on-wafer measurement results.

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian et al. proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results.

This paper proposes a detailed low frequency noise (LFN) parameter extraction method for high-voltage (HV) MOSFETs at low (50 mV) and medium (3 V) drain biases. In Vd = 3 V region, noise coming from the channel is dominant while in linear region there is an extra contribution of noise from the drift region part especially for long-channel devices in strong inversion region. Flicker noise of 50 V and 20 V N- and P-channel HV-MOSFETs was measured over a large current range from weak to strong inversion, making possible the extraction of the noise parameters related to the different noise contributions, such as mobility fluctuations in low current regime, carrier number fluctuations and Coulomb scattering in medium and high current regime. In some cases, series resistance noise contribution especially at high current is apparent as well. The parameter extraction procedure is devised for a recently established charge-based flicker noise model for HV-MOSFETs. Noise parameters related to the carrier number fluctuation effect in the gate oxide extension in drift region are also extracted in high current regime of long-channel devices under low drain bias condition. The frequency exponent AF related to the slope of the measured noise spectra is also extracted. Measurements and analysis include both long as well as short N- and P-channel HV-MOSFETs.

Unified transient and frequency domain noise simulation of random telegraph noise and flicker noise is conducted using a multiphonon-assisted model that considers tunneling probabilities and energy transitions of discretized traps in the gate insulator of MOSFETs. The proposed model is able to concurrently represent the dynamic behavior of electron and hole trapping and detrapping via interactions with both the Si substrate and Poly-Si gate. The model is implemented in a 3-D device simulator to examine the effect of device structure and bias conditions. The conventional analytical model does not precisely estimate the noise powers in short-channel MOSFETs due to the nonuniform trapped charge effect. The high trap density near the shallow trap isolation edges is predicted quantitatively by comparing the measured data with the simulated data. In conclusion, we confirm the validity of the developed unified simulator and its usefulness for gaining insights into trap sites and noise reduction engineering.

Here we report on the efficient detection of THz radiation generated from Ti:sapphire femtosecond laser system. The large-area interdigitated antenna is excited by optical pulses with pulse duration from 15 to 47 fs. We have tested two AlGaN/GaN HEMT-based THz detectors with integrated broadband antennas. Detectors are comparable in sensitivity but differ in applied parasitic signals elimination techniques. Despite being sensitive, the pick-up of the first detector without strong parasitic elimination exceeded the theoretically expected noise level about 100 times. For a second detector we have implemented more stringent interference avoiding techniques, such as gate shunting with a low resistance value resistor, and have managed to significantly improve system's detection capabilities. We have lowered a pick-up near to the thermal noise level and have extended signal/noise ratio to 26 dB.

We discuss the thermal noise and the effect of input noise sources on the output noise of plasmonic Field Effect Transistors operating in a quasi-ballistic regime. The input noise strongly affects the output noise at large signals and when the detectors operate near the threshold, where the highest responsivity is reached. In the detection regime with a finite drain current, 1/f noise becomes dominant at low noise frequencies, and similar mechanisms determine the contribution of the input noise to the output noise. The effect of the input noise in the plasmonic THz detectors on their output noise analyzed based on the numerical solution of the hydrodynamic equations is in qualitative agreement with the analytical model but reveals the importance of plasmonic ringing even in the devices with the extracted mobilities of 3500 cm2/Vs with the gate length of 130 nm. These results are important for designing plasmonic sensors using the frequency dependencies of the low frequency output noise for identifying different gas and liquid substances.

We propose a simple topology for the realization of ultra low noise differential-input, differential-output preamplifiers. The input devices can be either low noise JFET pairs (for high impedance sources) or low noise BJT pairs (for minimum low frequency voltage noise). Besides the input devices, the circuit requires only two matched low noise BJT transistor pairs (either PNP or NPN, depending on the input device type) and a few excess noise free resistors for consistently obtaining differential gains of 100 (40 dB) with a bandwidth in excess of 100 kHz and an equivalent input noise floor comparable to (or better than) those reported in the literature for similar devices. The preamplifier is to be regarded as an off-the-shelf component that can be employed as a building block for a number of applications in the field of low frequency noise measurements.

We present an investigation of shot noise in graphene-based Hall sensors, with the purpose of evaluating their detection limit and of developing strategies to improve their characteristics. We perform measurements on two devices, one with a defective contact that could however be used as a gate to control the carrier density in the device and the other with all contacts working. We discuss the results in terms of the dependence of the noise power spectral density on the carrier density and on the DC bias current. Finally, we provide an estimate of the detection limit, pointing out that the approach commonly used in the literature for its evaluation is flawed.

The standard DC and RF and characteristics were measured for the 28 nm p- and n- type MOSFETs. The charge based compact model EKV3 parameters were extracted and verified against measured data. Noise parameters for both n- and p-MOSFETs were measured and analyzed in terms of gate induced noise correlation with the drain current noise, short channel effects related noise. The PRC noise model as well as drain current and gate current noise spectral densities were extracted and analyzed. Measured harmonic distortion at 2.5, 5 and 8 GHz exhibits excellent linearity and in a perfect agreement with EKV3.

In this paper, we present a consistent perspective to interpret the channel noise of MOSFETs as suppressed shot noise for both long- and short-channel devices. We also derive an easy-to-use analytical equation for the shot noise suppression factor of MOSFETs working in the saturation region. The expression only relies on two process parameters - threshold voltage and effective oxide thickness, to predict the level of suppression for any CMOS technology. Together with the shot noise limit 2qI D , the suppression factor can accurately model MOSFET channel noise without invoking the channel length modulation effect. Moreover, we compare the modeled suppression factors with experimental values extracted from published experimental data in 180-nm and 40-nm technologies.

The transfer characteristic at room temperature of FinFETs processed for sub-10 nm technologies could always be explained by solving Poisson equation throughout the channel – dielectric interface. Various methods for the MOSFET parameters estimation are proposed in the literature. In this paper, the electrical parameters extraction technique based on the Y-function methodology is reminded. Low frequency noise is presented considering three major noise sources: 1/ f noise associated to carrier trapping-detrapping in the gate oxide, channel carrier mobility fluctuations and generation-recombination noise related to traps located in the depletion zone of the device. Theory and methodology in order to identify the 1/ f noise mechanism and to have information of the process induced traps in the silicon film using the noise spectroscopy technique are revisited.

Non-stationary, non-Gaussian noise severely limits the performance of narrowband (NB) power line communication (PLC) systems. Due to the periodic mains voltage, substantial parts of the noise are known to show time-periodic features. Exploiting these features can significantly improve noise canceling methods and thus the overall performance of PLC systems. A prerequisite for this is an accurate estimation of the statistical properties of the power line noise which is also an important part of the channel characterization. In this work, we perform a spectral correlation analysis to evaluate the strongest cyclic frequencies of the noise encountered in low-voltage NB-PLC applications. Our analysis is based on time-synchronized noise measurements at five different locations with a total observation time of 24 hours. Our contribution includes the implementation and estimation of the cyclic coherence function up to 500 kHz, the extraction of the strongest cyclic frequencies, as well as a short- and long-term analysis of the cyclic features. Finally, we present a statistical analysis of the cyclic frequencies based on the complete set of measurements. This analysis shows that cyclostationarity can be observed in the complete NB frequency range and confirms that the dominant cyclic frequency is twice the mains voltage frequency.

Although studies have investigated the effects of flicker noise on randomness, such effects demand further examination. Despite the random nature of flicker noise, a coloured distribution is observed in the power spectral density of flicker noise, indicating to a correlation in between adjacent samples. Studies have employed ring oscillators (ROs) that produce random numbers by sampling the digitised analogue signals of their outputs. This sampling procedure may change the spectral properties of flicker noise resulting from the folding effect of noise. Another topic of interest regarding sampled flicker noise is its random behaviour. To investigate the contribution of flicker noise, white noise, and their combination to randomness, we produce synthetic bit streams of these noise sources. From observations, we find that flicker noise contributes to the entropy of bit streams. Using the generated synthetic bit streams, we also explore the entropy dependence of a bit stream on the sampling period and analyse and compare the entropy levels of the outputs of ROs operating in strong and weak inversion. Results of the comparison demonstrate that only one RO operating in weak inversion may be sufficient to attain the required entropy level for qualifying the generated bit stream as random. The results of the analysis are also confirmed by measurements. In addition, the paper proposes an efficient design of a RO-based random number generator.

In this paper, a substrate-induced drain-current noise model is developed in addition to the channel thermal noise to explain the non-white-noise characteristic found in the measured drain-current noise in the gigahertz range. The substrate-induced drain-current noise model is derived from the proposed small-signal equivalent circuit with a substrate coupling network and a substrate thermal noise source. The model parameter extraction method utilizing Y-parameter analysis on the proposed small-signal equivalent circuit is demonstrated. The model for the total drain-current noise, the gate-current noise, their cross-correlation, and thereafter the four noise parameters is presented and verified experimentally. Excellent agreement between simulated and measured noise data has been obtained over different dimensions and operating conditions.

This paper presents a noise analysis in the frequency domain using noise power spectral density and considering the undersampling process coming from the native readout circuit sequence of image sensors. It reveals aliasing effect impacting the noise level of the image sensor. Key parameters of the undersampling process, such as sampling period, power spectral density level, and type, are explored. Low-frequency noise and particularly 1/f noise impact show a major impact in results. The new calculation algorithm is implemented in MATLAB software. Two CMOS image sensor technologies are used to perform a comparison between noise estimation and measurements. This comparison shows a very good correlation between estimations and measurements.

Current noise includes shot noise and thermal noise in realistic nano-MOSFETs,and shot noise can be acted by Fermi and Coulomb. Literatures either ignored shot noise suppression or only emphasized its existence without giving detailed analysis. In this paper, based on the Navid model, the expression of current noise in realistic nano-MOSFETs is derived. The model includes the suppression effects of Fermi exclusion and Coulomb interaction on shot noise. On this basis, the variations of current noise with channel length, temperature, source-drain voltage, and gate voltage are investigated. The results show that, when the channel length goes shorter or the temperature goes lower, the source-drain voltage becomes larger and the gate voltage becomes lower. The current noise is mainly shot noise.

A ballistic-electron transport-based semiconductor nanorectifier, also known as a ballistic rectifier, has been demonstrated to have an intrinsic zero threshold voltage. In this paper, we characterize its low-frequency noise properties and show that the zero-threshold property enables elimination of the flicker noise. As a potential terahertz detector, the ballistic rectifier exhibits a noise equivalent power in the range of commercially available, uncooled thermal terahertz detectors. The observed noise in the device at finite biases is modeled quantitatively. The derived simple formula reveals that the narrowest part of the electron channels has a dominant role in the device noise properties.

In order to maximize randomness of CMOS Ring Oscillators (RO) used in Random Number Generators (RNG), possibility of weak inversion operation of CMOS transistors is investigated. To predict weak inversion noise performance of RO, phase noise and jitter models of a CMOS RO in weak inversion operating region are obtained. Differential Ring Oscillator (DRO) and Inverter-based Ring Oscillator (IbRO) cases are both investigated. For each case, the model covers the flicker and the white noise component of phase noise and jitter. The derived models are verified by measurement results. 0.25 μm standard CMOS process has been used with a supply voltage of 0.7 V for DRO and 0.5 V for IbRO. Furthermore, phase noise and jitter behavior of a CMOS RO in strong and weak inversion region are compared through analytical models, simulations, and measurements. Even though white noise component of phase noise uses two different models for weak and strong inversion regions of operation, these two models exhibit continuity. Flicker noise component in weak inversion is much lower than the one in strong inversion, which also reduces the corner frequency. For a fair comparison of randomness performances, a randomness parameter is defined and randomness equations are derived for each case.

We present an analysis of electrical noise in III-V heterojunction TFET (HTFET). Using numerical simulations, random telegraph noise (RTN) amplitude induced by a single charge trap is investigated with regard to trap location, electron band-to-band-generation rate, bias, and transistor size. It is found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction. HTFET exhibits 40% less relative RTN amplitude at 0.3 V at gate lengths around 20 nm, over subthreshold Si-FinFET. RTN of HTFET at VGS=0 V is higher for a trap location at source-channel tunnel junction. To analyze flicker, shot, and thermal noise, we created transistor level Verilog-A-based electrical noise models. The results indicate HTFETs competitive noise performance in megahertz frequency range, over Si-FinFET. In the range 10 GHz or more with operating voltages exceeding 0.3 V, HTFET input noise is worse due to the dominance of shot noise. A differential amplifier with active load is used to examine the electrical noise performance at circuit level. We emphasize that high intrinsic gain, drive current, and output resistance of HTFET can be used to achieve superior mixed signal performance metrics in HTFET design over Si-FinFET design, at an improved electrical noise performance.

The phase noise of a ring oscillator can be obtained by multiplying its open-loop phase noise by a simple shaping function. The shaping function is computed using first principles and is applicable to both flicker-noise-induced and white-noise-induced phase noise, leading to compact equations for ring oscillators. It is also shown that flicker noise upconversion in ring oscillators is primarily a function of the total gate capacitance and inevitable regardless of the risetime and falltime symmetry. Two oscillator prototypes fabricated in 65-nm CMOS technology verify the validity of the results.

For a 4T pixel-based CMOS image sensors (CIS) readout chain, with column-level amplification and CDS, we show that the input-referred total noise in a standard 65 nm process can be reduced to 0.37 e− rms . Based on transient noise simulation using Eldo, the deep sub-electron noise performance have been reached using only circuit techniques and optimal device choices. The simulation results have been favorably compared with analytical noise calculations. The shot noise associated to the gate tunneling current has been simulated and the possibility of photoelectron counting in this 65 nm process has been demonstrated.