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The low frequency (LF) noise has been studied in n-channel triple-gate bulk fin Field-Effect Transistors (FinFETs), which are developed for one-transistor (1T) memory applications. Significant variation in the noise spectral density has been observed, which is related to the random occurrence of excess Lorentzian components, associated with generation–recombination (GR) noise. Both gate-voltage-dependent and gate-voltage-independent GR noise peaks have been found, which are assigned to gate oxide traps or traps in the silicon fins, respectively. In addition, excess \1/f noise in weak inversion has sometimes been observed and is ascribed to surface-roughness fluctuations. Overall, the gate oxide quality seems to be the major contributor to the LF noise and not the channel and source–drain engineering investigated here. [ABSTRACT FROM PUBLISHER]

This work investigates the effects of high-energy neutrons and γ-rays on multiple-gate FETs with different geometries (notably gate lengths down to 50 nm). The impact of radiation on device behavior is addressed through the variation of parameters such as threshold voltage, subthreshold slope, transconductance maximum and DIBL. It is shown that degradations caused by γ-rays and high-energy neutrons with similar doses are largely similar. It is revealed that, on the contrary to the generally-believed immunity to irradiation, very short-channel FinFETs can become extremely sensitive to the total dose effect. The possible reasons are discussed. [ABSTRACT FROM AUTHOR]

Abstract: In this paper specific features of the multiple-gate MOSFETs (MuGFETs) behavior at high temperatures (up to 300°C) are analyzed through measurements, 2D simulations and analytical models of long-channel transistors. The high-temperature evolutions of threshold voltage and subthreshold slope are discussed paying particular attention to the influence of Si film thinning. High-temperature behavior of the threshold voltage and subthreshold slope in MuGFETs is demonstrated, for the first time, to be different from those generally considered for FD SOI MOSFETs. It is shown that the threshold voltage shift with temperature is strongly attenuated in MuGFETs and further decreases with Si film thinning. Then, the deviation of the MuGFET subthreshold slope at high temperatures from the expected ideal linear temperature dependence is analyzed and the possible reasons are discussed. [Copyright &y& Elsevier]

Conventional charge pumping is demonstrated on triple-gate silicon-on-insulator FinFET gated-diode structures with varying fin widths. A simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density. A higher interface state density on the sidewalls is observed, which is attributed to higher fin sidewall roughness. The methodology is also demonstrated to be sensitive to fin sidewall surface crystallographic orientation. The technique presents a straightforward means of assessing the fin sidewall and topwall interface quality, which can then be directly correlated with both processing influences and reliability effects. [ABSTRACT FROM AUTHOR]

Abstract: This paper investigates, for the first time, the influence of high-energy neutrons on Multiple-Gate FETs (MuGFETs) with various gate lengths and fin widths. Neutron-induced degradation is addressed through the variation of major device parameters such as threshold voltage, subthreshold slope, maximum transconductance and DIBL. We demonstrate that high-energy neutrons result in total-dose effects largely similar to those caused by γ- and proton-irradiations. It is shown that, contrarily to the generally-believed immunity to irradiation, very short-channel MuGFETs can become extremely sensitive to the total-dose effect. The possible reasons of such length-dependent neutron-induced degradation are discussed and finally related to gate edges. [Copyright &y& Elsevier]

Abstract: In this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field effect transistors (FinFETs) with high-k dielectric and metal gate. Our results indicate that with decreasing fin width the well-known performance improvement in terms of sub-threshold swing and drain-induced barrier lowering are accompanied by a degradation of the variability and the reliability. As a matter of fact fin width scaling causes (i) higher hot-carrier degradation (HC) in nFinFETs owing to the higher charge carrier temperature for the same internal stress voltages; (ii) worse negative bias temperature instability (NBTI) in pFinFETs due to the increased contribution from the (110) surface; (iii) higher variability due to the non-uniform fin extension doping, as highlighted by applying a novel characterization technique. [Copyright &y& Elsevier]

Abstract: In this paper, the appearance of gate induced floating body effects in triple gate SOI nFinFETs with TiN/SiON and TiN/HfO2 gate stacks is investigated. Different floating body effects (FBEs) are found to appear under moderate accumulation back gate bias (V BG) conditions in devices with wide and long enough geometries. In particular, a second peak in the linear transconductance (g mf), associated with electron valence band (EVB) direct tunneling, is observed in TiN/SiON devices for front gate voltages (V FG) around 0.8V. Interestingly, in spite of showing about two orders of magnitude lower total gate current, a second peak in g mf is also found in TiN/HfO2 devices for V FG around 1.1V. Under the accumulation V BG conditions in which FBEs are observed, front gate switch drain current (I D) transients are also appreciated. Interestingly, a change in the shape of I D transients is observed for V FG conditions in which EVB majority carriers are injected into the floating fin. The I D transients, as well as the second peak of g mf and other FBEs, are found to gradually diminish for strong accumulation V BG conditions or reduced geometry dimensions. [Copyright &y& Elsevier]

Abstract: In this work the analogue performance of 50nm gate length FinFETs is investigated under static and dynamic conditions up to 110GHz. The fin width is shown to have a large impact on some analogue figures of merit such as the Early voltage because it determines the existence of volume inversion, full or partial depletion inside the fins. The RF measurements show that a non-uniform silicidation of the three-dimensional polysilicon gate can have a strong impact on the device maximum frequency of oscillation (f max). However, it is also shown on the basis of experimental and modelled data that process optimization on the gate side as well as source/drain engineering should lead to f max values higher than 250GHz, making FinFETs very promising devices for future use in RF applications. [Copyright &y& Elsevier]