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Abstract: This work will focus on the use of Selective Epitaxial Growth (SEG) of Si and SiGe in multi-gate devices. We will demonstrate the necessity of using SEG in the processing of these narrow fin devices. Reductions of the source/drain resistance and Gate Induced Drain Leakage (GIDL) are the main advantages of using SEG. Although the use of SiGe SEG has little impact as mobility booster in narrow fin pMOS devices, it provides a significant reduction in contact resistance. [Copyright &y& Elsevier]

In this letter, we investigate the impact of a hybridized strain technology on the performance of FinFET-based multigate field-effect transistors (MUGFETs). The technology combines the use of supercritical strained-silicon-on-insulator (SC-SSOI) and strained contact etch stop layers (CESLs). We will show that SC-SSOI (top plane orientation (100)/(110)) with tensile CESL (tCESL), when used for MUGFET, leads to higher improvement in electron mobility as compared to standard SOI with tCESL. Therefore, the combination of both mobility boosters is very beneficial for n-channel MOS MUGFET. However, the impact of compressive CESL on p-channel MOS (pMOS) performance is strongly reduced and becomes even negative when used on an SC-SSOI substrate. Local strain relief of the SC-SSOI substrate is mandatory in order to achieve good pMOS device performance. [ABSTRACT FROM AUTHOR]

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current. [ABSTRACT FROM AUTHOR]

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (Wfin = 10 nm) and tall (Hfin = 60-80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain. induced barrier leakage characteristics of 45 mV/V at Vdd = 1 V and Lg = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the VT at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (Wfln = 65 nm) with Idsat = 380 µA/µm at Ioff = 60 nA/µm and Vdd = -1.2V. [ABSTRACT FROM AUTHOR]

Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm. [Copyright &y& Elsevier]

In this work, we will give an overview of the innovations in materials and new device concepts that will be needed to continue Moore’s law to the sub-10 nm technology nodes. To meet the power and performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS. [ABSTRACT FROM AUTHOR]

Abstract: This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110nm long channel achieve an intrinsic gain of 25dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body. [Copyright &y& Elsevier]

Abstract: In this work, we extend the modified shift and ratio method, originally used for extracting the effective channel length in standard short channel MOSFETs, to the extraction of the fin width in FINFET devices. Using devices with different fin widths, the electrical width of the devices can be extracted. The method is adapted in such a way that it takes into account the difference in mobility due to the different crystal orientation of the fin sidewalls and top surface, the width dependence of the threshold voltage and the influence of the increasing source/drain resistance for narrow fin devices. [Copyright &y& Elsevier]