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FPGA-based digital IC test equipment is a promising solution for low to mid-end applications. In the past, several FPGA data/timing formatters have been demonstrated to generate test waveforms at 100 MHz symbol rate and 200 ps or better resolution. In this paper, an FPGA-based test response receiver for digital IC testing is proposed. First, a three-stage round-trip-delay compensation scheme is introduced so that the strobe window can fully cover the test response window. Then, the corresponding characterization and calibration techniques are developed for the programmable delay line and roundtrip-delay. A prototype receiver is implemented on a Xilinx Spartan 6 FPGA; measurement results show that it is capable of 100 MHz sampling rate with 200 ps strobe position resolution.

The data/timing formatter is a key module in automatic electronics test equipment; it formats the test data to the desired wave shape and places the timing edges at the designated locations. In this work, we investigate the design and implementation of the FPGA-based data/timing formatter. Compared to its ASIC counterpart, the FPGA-based formatter is more flexible because it can be reconfigured to best fit the target test specifications. However, routing uncertainty and limited types of available logic and interconnect resources also pose great challenges. This work proposes a formatter design that is suitable for FPGA implementation. Several high-linearity FPGA-based programmable delay lines are developed. According to its characteristics, each type of delay lines is assigned a different role in the formatter. The formatter is also equipped with a calibration unit to further improve the edge placement resolution and accuracy. A 100-Msps FPGA-based data/timing formatter with 20-ps edge placement resolution has been implemented on an FPGA development board to validate our ideas.

FPGA-based digital IC testers have been commercialized and shown to be a promising solution for low to mid-end applications. For FPGA-based test equipment to be a practical solution, it is crucial to increase the number of channels that one single FPGA can accommodate. The objective of this work is to develop a data/timing formatter architecture that consumes less FPGA resources so as to accommodate 16 formatter channels in one Xilinx Spartan 6 FPGA. To reach this goal, the proposed formatter utilizes the more compact time/format set tables to store the pre-processed control signals and delay codes required for symbol generation. To match the time/format set table based symbol generation, a new EG (edge generator) pool structure is developed; it also lowers FPGA resource usage without sacrificing the timing accuracy. Furthermore, the EG is redesigned to reduce the controller timing complexity. The proposed 16-channel formatter has been implemented on a Xilinx Spartan 6 FPGA. Compared to the previously reported 5-channel formatter, it delivers the same performance (200 ps edge placement resolution and 100 MSPS symbol rate) without significant increase in FPGA resource usage.

With modern FPGAs' reconfiguration flexibility and abundant resources, FPGA-based test equipment has become a promising solution for low to mid-end test and measurement applications. However, FPGA structure and specifications limit the choice of tester architecture and achievable performance. In this paper, we design and implement an FPGA-based multi-channel data/timing formatter, a key component in automatic test equipment. The proposed formatter (1) adopts the EG (edge generator) pool concept to improve hardware utilization, (2) employs accuracy-driven EG scheduling to improve edge placement accuracy, (3) embeds a delay monitor for temperature compensation, and (4) allows inter-channel skew adjustment. A prototype five-channel formatter is implemented on Xilinx Spartan-6 FPGA. The per channel symbol rate is 100 Msps and the edge placement resolution is 200 ps.