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Advanced devices are not only driven by minimum device geometry, performance enhancement, and cost issues, but also require a low power consumption. Device scaling for higher performance and lower power consumption necessitates the introduction of advanced process modules, new materials new device architectures and, finally, even the use of alternative device operation principles compared to the standard MOS transistor. Several of these advanced devices will be discussed in view of their scalability and their potential for coping with the ITRS roadmap. Key performance parameters will be investigated. [ABSTRACT FROM AUTHOR]

An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation ( $\Delta N$ ) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation. [ABSTRACT FROM PUBLISHER]

In this paper, we have fabricated high-performance Si0.45Ge0.55 implant-free quantum well (IFQW) pFET with embedded SiGe source/drain stressor. This device showed high drive current of 1.28 mA/ \mu m at I_{\mathrm {\scriptstyle OFF}\_{D}} of 160 nA/ \mu $ m with channel length/width of 30 nm/0.16 $\mu $ m ( $V_{{\rm {DD}}} =-1$ V). Conventional ion-implanted extension is replaced with in situ boron-doped epitaxial Si0.75Ge0.25 layer. This enables lower process temperature which can maintain an integrity of Si0.45Ge0.55 film and thus higher hole mobility. In narrower width devices, we observed significant hole mobility boost ( $1.9\times $ improvement from active width of 10 to $0.1~\mu $ m). This is due to the relaxation of unwanted transverse stress in Si0.45Ge0.55 channel applied from Si substrate. IFQW devices show improved short channel control thanks to the epitaxially formed raised extension structure compared with conventional devices which have implanted extension. Achieved device performance is one of the best among all Si1–xGex-based channel pFET up to date. [ABSTRACT FROM AUTHOR]

Endurance is investigated on one transistor floating body RAM cells processed on a silicon-on-insulator substrate with ultrathin buried oxide, and programmed using the bipolar junction transistor current inherent in MOSFETs. During the hole generation step, defects are generated close to the drain. These defects not only reduce the retention time but also result in a lower hole generation rate as a function of the number of cycles, which leads to a write 1 failure. We have shown that standard junction devices with a lightly doped drain (LDD) region are more enduring than extensionless devices with the LDD left undoped. This is owing to the poor spacer oxide on top of the extensionless region where holes are generated. [ABSTRACT FROM PUBLISHER]

Through a combination of electrical measurements, technology computer-aided design simulations, and wafer bending experiments, the effect of elastic stress relaxation on the layout dependence of \Si1-x\Gex\-channel p-channel field-effect transistors (pFETs) is studied. This work focuses on scaling of the transistor width W, the active-area length (length of diffusion, LOD) for isolated transistors, and poly-to-poly length LP/P of nested configurations. A strong narrow-width current enhancement is reported, even for relatively large widths, above 100 nm. On the other hand, the layout dependence on LOD or LP/P is also predicted but only for aggressively scaled layouts (LOD or LP/P below 100 nm). W and LP/P scaling lead to current enhancement, whereas LOD scaling is expected to degrade performance. No significant dependence of short-channel threshold voltage on W, LOD, or LP/P was observed. This study indicates that, as higher germanium concentrations of the channel lead to more layout dependence, this concentration may need to be optimized carefully to combine high channel mobility with limited added design complexity. Moreover, the channel thickness should be kept as thin as possible, as layout dependence is enhanced for thicker channels. [ABSTRACT FROM PUBLISHER]