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As one type of associative memory, content-addressable memory (CAM) has become a critical component in several applications, including caches, routers, and pattern matching. Compared with the conventional CAM that could only deliver a “matched or not-matched” result, emerging multilevel CAM (ML-CAM) is capable of delivering “the degree of match” with multilevel distance calculation. This feature has been desired in applications that need beyond-Boolean matching results. However, existing ML-CAM designs are limited by the bit-cell device discharging current mismatch and vulnerability to the timing of sensing operations for distance calculation. This inherent constraint makes it difficult to further improve the accuracy and scalability toward higher accuracy and higher dimension matching. In this work, we propose CapCAM, a multilevel Capacitive Content Addressable Memory. It could be implemented based on either static random-access memory (SRAM) or emerging technologies, e.g., the ferroelectric field-effect transistor (FeFET). CapCAM could provide linear and stable voltage drop scaled by the match degree and need no strict timing for result sensing, which embraces the high-accuracy and high-scalability search. The inherent enabler of CapCAM is the charge-domain computing mechanism. This article will present the basic concept, operating mechanisms, detailed circuit designs, and circuit-level simulations of CapCAM. Besides, we apply CapCAM to few-shot learning applications and compare CapCAM with the current-domain TCAM designs. Results show 99.2% accuracy for a five-way five-shot classification task with our proposed CapCAM design while considering 1-fF capacitors, 20-domain FeFETs, and 256 columns. In contrast, the prior work based on discharging dynamics requires strict timing controls and suffers from accuracy degradation under the same configuration, which demonstrates CapCAM’s capability of low-power, accurate, and scalable multilevel CAM (ML-CAM) computing. [ABSTRACT FROM AUTHOR]

Emerging voltage reference generators (VRGs) are of great demand for low-power applications in recent years. However, keeping good linearity for VRGs in deep submicrometer process is still challenging. Negative capacitance field-effect transistor (NCFET) is an emerging device, which has been found with a negative differential resistance (NDR) phenomenon and has the potential to be applied in VRGs to optimize their linearity. Hence, the feasibility of using NCFET in an emerging ultralow-power (ULP) VRG is studied in this work. An empirical formula to describe NCFET’s NDR is proposed and verified by simulation through a compact SPICE model based on the Landau–Khalatnikov (LK) equation. By adjusting the strength of NDR of NCFET, its output differential resistance can be changed and cancel out the positive differential resistance (PDR) of CMOS transistor. Therefore, the proposed NCFET-based VRG achieves higher linearity. The simulation results show that the line regulation of the NCFET-based VRG decreases from 2.25%/V to 0.21%/V ($10\times $). [ABSTRACT FROM AUTHOR]

In this article, we analyze the impact of process variations of the ferroelectric film on the performance of the negative capacitance field-effect transistor (NCFET). Variations of the ferroelectric layer area (resulting from the variation of the transistor dimension sizes and the edge-effect), the ferroelectric layer thickness, the polarization, and the coercivity are taken into consideration to evaluate the impact on the NCFET performance. These results can serve as a guideline to improve both the circuit performance and yield for analog and digital circuits. To showcase this ability, the influence of these variations on the oscillating frequency of a five-stage ring oscillator and the mirroring current of a current mirror are analyzed. The results show that the distribution of the standard derivation of the oscillating frequency is 1.9 MHz on condition of TFE = 14 nm, WP/LP = 1μm/45 nm, and WN/LN = 500/45 nm, and the standard derivation of the mirroring current is 0.17μA on condition of W = 1 μm, L = 500 nm, and TFE = 20 nm. [ABSTRACT FROM AUTHOR]

In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated. [ABSTRACT FROM AUTHOR]

In this letter, the write disturb of Hf0.5Zr0.5O2-based 1T-FeFET nonvolatile AND memory array is experimentally investigated for ${V}_{W}$ /2 and ${V}_{W}$ /3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low- ${V}_{\textsf {TH}}$ erased state and the increased read current of the high- ${V}_{\textsf {TH}}$ programmed state are the key factors that limit the maximum array size. [ABSTRACT FROM AUTHOR]

This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (B&R), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule B&R energy. This new nvDFF promises area- and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications. [ABSTRACT FROM AUTHOR]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

Nonvolatile SRAM (nvSRAM) has emerged as a promising approach to reducing the standby energy consumption by storing the state into an in situ nonvolatile memory element and shutting down the power supply. Existing nvSRAM solutions based on a nonvolatile backup in magnetic tunnel junction and ReRAM, however, are costly in backup and restore energy due to static current. This cost results in a long break-even time (BET) when compared with a lowered voltage standby volatile SRAM. This brief proposes an nvSRAM based on ferroelectric FETs (FeFETs) that are capable of fully avoiding such static current. A simple differential backup and restore circuitry is proposed, achieving sub-fJ/cell total energy per backup and restore operation at the 10-nm node. This leads to hundreds of times BET improvement over existing ReRAM nvSRAM solutions. This nvSRAM also indicates the future FeFET design trends for such memory-logic synergy. [ABSTRACT FROM PUBLISHER]

Steep-slope heterojunction tunnel field-effect transistor (HTFET) devices promise new opportunities beyond CMOS in low-power high-performance communication applications. In this paper, the circuit design optimization of a low-power 14-bit 1-GS/s current-steering digital-to-analog converter (DAC) using 0.4/0.3 V mixed-supply HTFETs is explored. Based on the device characteristics comparison and circuit analysis, it is shown in this paper that HTFET endorses significant differences in both $I$ – $V$ and $C$ – $V$ due to the steep-slope tunneling mechanism and a nature of vertically fabricated structure. While such differences significantly affect the circuit design corners, this paper gives the device-circuit co-optimization for the HTFET DAC, reaching at higher current source output impedance, less nonlinear switching glitch distortions, and thus superior spectral performance over the Si-CMOS DAC. HTFET device variation is also discussed, and calibration techniques are adopted for the static matching accuracy. [ABSTRACT FROM AUTHOR]

This paper explores the energy efficiency advantage of a 6-bit III-V heterojunction tunnel field-effect transistor (HTFET) based successive-approximation register (SAR) analog-to-digital converter (ADC) with 20-nm gate length. Compared with the Silicon FinFET (Si FinFET) ADC, the HTFET SAR ADC achieves approximately 3 times power consumption reduction and 6 times size reduction. Signal-to-noise and distortion ratio is 31.4 dB for the HTFET SAR ADC, which is 2.81 dB higher than the Si FinFET ADC due to the decreased quantization noise rising from the high ON-current characteristic of HTFET at low supply voltage. The energy per conversion step for both HTFET and Si FinFET ADC designs are 0.43 and 1.65 fJ/conversion-step, respectively, at a fixed supply voltage of 0.30 V. [ABSTRACT FROM AUTHOR]

This letter reports the first demonstration of 101 kV trenched-and-implanted normally off 4H-SiC vertical junction field-effect transistor (TI-VJFET) with a 120 µm ∼4.9 × 1014 cm-3-doped drift layer. Blocking voltages (VB) of 10 kV to 11 kV have been measured. The best specific on-resistance (RSP-ON) normalized to source active area has been determined to be 130 mΩ · cm². Three-dimensional computer modeling including current spreading effect shows that the TI-VJFET would have a specific resistance of 168 mΩ · cm² if it is scaled up substantially in size. [ABSTRACT FROM AUTHOR]