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In the current work, a design space for developing the performance enhanced strain-engineered Si nanowire field-effect-transistors has been provided. The fraction of insertion of the nanowire channel into the Insulator-on-Silicon substrate with judicious selection of high-k gate insulators is used as the key design parameter. The combined effect of fractional insertion and gate insulators results in inducing stress into the nanowire channel and, depending on their selection, it changes from tensile to compressive. Such induced-stress alters the existing inherent phononic-stress, leading to the modification of the carrier transport in the device channel. The carrier transport behavior in such partially embedded nanowire FETs has been modeled by incorporating the relevant stress-related effects into the indigenously developed self-consistent quantum-electrostatic framework. These equations are solved by employing the non-equilibrium Green's function formalism. The study shows the phonon scattering under tensile strain to occur at the expense of electron energy; however, the electrons can also gain energy during such scattering in compressive stress. Thus, the device current has been observed to increase with tensile stress and it achieves relatively smaller values when the inherent tensile phononic stress is balanced by the induced compressive stress. However, the current is finally observed to increase once the compressive stress overcomes the inherent tensile phononic stress. In general, the present devices exhibit promising Ion/Ioff ratio for all of the fractional insertions and gate dielectrics with a maximum Ioff of <10 nA/μm, threshold voltage of sub-0.3 V, gm of ∼104 µS/µm, sub-threshold swing of ∼100 mV/dec, and drain-induced-barrier-lowering of ∼100 mV/V. [ABSTRACT FROM AUTHOR]

The continuously intensifying demand for high-performance and miniaturized semiconductor devices has pushed the aggressive downscaling of field-effect transistors (FETs) design. However, the detrimental short-channel effects and the fundamental limit on the sub-threshold swing (SS) in FET have led to a drastic increase in static and dynamic power consumption. The operational limit of nanoscale transistors motivates the exploration of post-CMOS devices like Tunnel FET (TFET), having steeper SS and immunity toward short channel effects. Thus the field of nanoscale 2D-TFET has gained compelling attention in recent times. The nanoscale TFET, with two-dimensional (2D) semiconductor materials, has shown a significant improvement in terms of higher on-state current and lower sub-threshold swing. In this context, the review presented here has comprehensively covered the gradual development and present state-of-arts in the field of nanoscale 2D-TFET design. The relative merits and demerits of each class of 2D materials are identified, which sheds light on the specific design challenges associated with individual 2D materials. Subsequently, the potential device/material co-optimization strategies for the development of efficient TFET designs are highlighted. Next, the experimental development in 2D-TFET design is discussed, and specific synthesis/fabrication challenges for individual material systems are indicated. Finally, an extensive comparative performance study is presented between the simulated as well as experimentally reported potential 2D materials and state-of-the-art bulk material-based TFETs. [ABSTRACT FROM AUTHOR]

An analytical model including the simultaneous impact of lattice and thermo-elastic constant mismatch-induced stress in nanowires on Insulator-on-Silicon substrate is developed. It is used to calibrate the finite-element based software, ANSYS, which is subsequently employed to estimate process-induced stress in the sequential steps of NW-FET fabrication. The model considers crystal structures and orientations for both the nanowires and substrates. In-plane stress components along nanowire-axis are estimated for different radii and fractions of insertion. Nature of longitudinal stress is observed to change when inserted fraction of nanowires is changed. Effect of various high-k gate-dielectrics is also investigated. A longitudinal tensile stress of 2.4 GPa and compressive stress of 1.89 GPa have been obtained for NW-FETs with 1/4th and 3/4th insertions with La 2 O 3 and TiO 2 as the gate-dielectrics, respectively. Therefore, it is possible to achieve comparable values of electron and hole mobility in NW-FETs by judiciously choosing gate-dielectrics and fractional insertion of the nanowires. [ABSTRACT FROM AUTHOR]

In the current work, the impact of electron-phonon scattering phenomena on the transport behaviour of silicon nanowire field-effect-transistors with sub-mean free path channel length has been investigated by developing a theoretical model that incorporates the responses of carrier effective mass mismatch between the channel and source/drain. For this purpose, a set of relevant quantum field equations has been solved by non-equilibrium Green's function formalism. The obtained device current for a particular set of biases is found to decrease due to phonon scattering below a certain doping level of source/drain, above which it is observed to enhance anomalously. Analyses of the quantified scattering lifetime and power dissipation at various confinement modes of the device indicates that such unusual enhancement of current is originated from the power served by phonons instead of associated decay processes. The power generation has been observed to improve by using high-k materials as gate insulator. Such results may contribute significantly to the future nano-electronic applications for energy harvesting. [ABSTRACT FROM AUTHOR]

Dielectrically modulated tunnel FET (DMTFET)-based biosensors show higher sensitivity but lower subthreshold current compared with their dielectrically modulated FET counterpart. In this context, the effect of use of silicon–germanium (SiGe) source and n+-pocket-doped channel is investigated with the help of extensive device-level simulations. This paper explores the underlying physics of germanium composition variation in the source region, and doping concentration variation in n+-pocket region, from the perspective of biomolecule conjugation. The effects of source bandgap and tunneling length over the band-to-band tunneling component have been analyzed, and, subsequently, the sensing performance of DMTFETs has been estimated. The results show that SiGe-source DMTFET has significant superiority over n+-pocket DMTFET for attaining higher subthreshold current level while retaining acceptable sensitivity. Such sensitivity-current optimization has been studied for different gate and drain biases, and the suitable biasing range of operation has been indicated. In addition, the relative efficiency of SiGe source and n+-pocket-doped channel has been studied under different biomolecule sample specifications. Finally, the influence of trap-assisted tunneling on DMTFET sensing performance has been analyzed, and the comparative role of SiGe source and n+ pocket has also been indicated in this context. [ABSTRACT FROM AUTHOR]

In this paper, a novel device structure, operating on the principle of band-to-band tunneling, has been designed for near-infrared (1– 1.5~\mu \textm ) multispectral optical sensing applications. A drain current model based on line tunneling approach has been developed to illustrate the device operation. The results of the model are compared with the simulated data for devices with similar dimension and structure, indicating good accuracy of the developed model. Spectral response of the device is studied by estimating the relative values of its transfer—as well as output—characteristics, and also by measuring the variation of threshold voltage, VT and ON-state current, I\mathrm{{\scriptscriptstyle ON}} . VT and I\mathrm{{\scriptscriptstyle ON}} are found to be sensitive to wavelength variations at moderate gate doping levels. VT is found to increase by $\sim 40$ mV and I\mathrm{{\scriptscriptstyle ON}} decreases by 35% for a change of illumination wavelength from 1 to 1.5 \mu \textm at a gate doping of 1 \times 10^18 cm ^-3 . Peak spectral sensitivity at an illumination intensity of 0.75 W/cm ^2 is found to be 318.38, 2.02 \times 10^3 , and 672.2 corresponding to the change in wavelength from (1–1.2 \mu \textm ), (1.2–1.45 \mu \textm ), and (1.45–1.5 \mu \textm ), respectively. [ABSTRACT FROM AUTHOR]

Surface channel strained-silicon MOSFETs on relaxed Si1-x Gex virtual substrates (VSs) have been established as an attractive avenue for extending Si CMOS performance as dictated by Moore's law. The performance of a surface channel Si n-MOSFET is significantly influenced by strained Si/SiO2 interface quality. The effects of Ge content (20, 25, and 30%) in the VS and strained-Si thickness (6, 5.5, 4.7, and 3.7 nm) on the strained Si/SiO2 interface have been investigated. The interface trap density was found to be proportional to the Ge content in the VS. Fixed oxide charge density reduces to a lower limit at higher strained-Si thickness for any Ge content in the VS, and the value increases as the strained-Si thickness is reduced. There is a high concentration of interface trap charge and fixed oxide charge present for devices with a strained-Si channel thickness below 4.7 nm. To investigate the effect of strained Si/SiO2 interface quality on MOSFET devices fabricated using a high- temperature CMOS process, the performance of surface channel n-MOSFETs has been correlated with channel thickness. It is noted that the drain-current rapidly decreases at low gate voltages for channel thicknesses less than 4.7 nm. The performance of both MOS capacitors and MOSFETs degraded below a strained-Si thickness of 4.7 nm irrespective of the Ge content in the VS even up to 30%. TCAD simulations have been carried out to analyze the effect of strained Si/SiO2 interface on electrical characteristics. Performance degradation in thin strained-Si channels is primarily attributed to gate oxide quality. The out-diffused Ge accumulates at the strained Si/SiO2 interface, introducing a significant amount of interface traps and fixed oxide charges during thermal oxidation. Interface trap density and fixed oxide charge density significantly increased when the Ge concentration at the surface becomes more than 6%. This paper suggests that a minimum strained-Si layer thickness of 5.0 nm is required to achieve a good strained Si/SiO2 interface quality for surface channel strained-Si n-MOSFETs, fabricated using a high thermal budget CMOS process. [ABSTRACT FROM AUTHOR]

In this work, a modified Fin shaped Field Effect Transistor (FinFET) structure has been proposed with dual SiGe embedded extended source regions. Comparative simulation studies with SiGe embedded source/drain conventional single Fin channel and dual Fin channel FinFET structure having similar device footprint area shows almost 3× and 1.5× improvement of drive current respectively and lower threshold voltage in the proposed architecture. The dual extended SiGe source regions and presence of Si drain in the vertical direction of the channel generate bi-axial channel stress which improves the channel charge density, which results in improvement in drive current significantly. Also it has been observed from various simulation studies that the separated gate regions increase the inversion current density in the channel which also leads to improvement of the device performance. [ABSTRACT FROM AUTHOR]