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A DAQ architecture for a PET system is presented that focuses on modularity, scalability and reusability. The system defines two basic building blocks: data acquisitors and concentrators, which can be replicated in order to build a complete DAQ of variable size. Acquisition modules contain a scintillating crystal and either a position-sensitive photomultiplier (PSPMT) or an array of silicon photomultipliers (SiPM). The detector signals are processed by AMIC, an integrated analog front-end that generates programmable analog outputs which contain the first few statistical moments of the light distribution in the scintillator. These signals are digitized at 156.25 Msamples/s with free-running ADCs and sent to an FPGA which detects single gamma events, extracts position and time information online using digital algorithms, and submits these data to a concentrator module. Concentrator modules collect single events from acquisition modules and perform coincidence detection and data aggregation. A synchronization scheme over data links is implemented that calibrates each link’s latency independently, ensuring that there are no limitations on module mobility, and that the architecture is arbitrarily scalable. Prototype boards with both acquisition and concentration functionality have been built for evaluation purposes. The performance of a small PET system with two detectors based on continuous scintillators is presented. A synchronization error below 50 ps rms is measured, and energy resolutions of 19% and 24% and timing resolutions of 2.0 ns and 4.7 ns FWHM are obtained for PMT and SiPM photodetectors, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents a flexible filter and control unit structure for implementing different VLSI architectures on two-dimensional DWT. These structures are applied over three different architectures: a direct approach, Recursive Pyramidal Algorithm (RPA) architecture, and a new proposed modification of RPA. This modified architecture works in a non-separable fashion using a parallel filter structure with distributed control to compute all the DWT resolution levels. It is fully modular and scalable, with low latency and high throughput performance. Implementation results based on a Virtex-II FPGA device are included. Real-time video processing is achieved. [Copyright &y& Elsevier]