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3 results on '"Kalra, Dheeraj"'

1. Realization of CMOS 0.18 µm Low Noise Amplifier for 2–5 GHz Using Cascode-Cascade Topology

Author

Kalra, Dheeraj, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Kumar, Jitendra, editor, and Jena, Premalata, editor

Published
2021
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3. Mutually coupled dual-stage RC feedback LNA for RF applications.

Author

Kumar, Manish, Kalra, Dheeraj, and Shukla, Aasheesh

Subjects
*LOW noise amplifiers, *CIRCUIT complexity, *REFLECTANCE, *POWER resources, *ENERGY consumption
Abstract

The designed circuit features a dual-stage Low Noise Amplifier (LNA) in which, a common source (CS) configuration is employed to achieve high gain, while the subsequent stage adopts a Complementary Common Gate (CCG) setup provide the low power consumption. This arrangement ensures that both transistors share the same biasing current, promoting energy efficiency. The two stages are interconnected in a cascade configuration, amplifying the overall gain and concurrently mitigating noise. To facilitate wideband matching in the input stage, a parallel RC feedback mechanism is implemented. Additionally, a pair of mutually coupled inductors in the CS and CCG stages contribute to rendering the input impedance exclusively resistive, concurrently minimizing the overall size of the circuit. All simulations were done using 65 nm CMOS technology in Cadence Virtuoso. The proposed LNA showcases a Noise Figure (NF) of 3.2 dB, a Peak Power Gain (S21) of 19.8 dB, and an input reflection coefficient (S11) of –16.2 dB, spanning a bandwidth of 3.1-6.2 GHz. Operating on a 1V power supply, the proposed LNA demonstrates power efficiency by consuming only 2.8 mW. The overall performance assessment of the LNA is gauged using the Figure of Merit, yielding an obtained value of 18.2. Comparative analysis with other cutting-edge designs is presented in Table 1. [ABSTRACT FROM AUTHOR]

Published
2024
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