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The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods. [ABSTRACT FROM AUTHOR]

Wafer map defect pattern recognition is an indispensable part in the semiconductor manufacturing process. Wafer map defect pattern recognition and classification can locate the cause of failures in the manufacturing process. In this study, we propose a deep convolutional neural network architecture incorporating improved convolutional block attention module (I-CBAM) for pattern recognition and classification of single-type wafer map defects. The proposed method consists of three steps: First, a multi-branch attention module is designed, which focuses more on the main information of defect clusters, extracts richer feature information, and improves feature extraction capabilities. Secondly, I-CBAM is integrated into the ResneXt50 backbone network to extract wafer map defect features. Finally, the extracted features are fed to a support vector machine combined with an error-correcting output code to classify the wafer map defect pattern. The experimental results on the real-world datasets WM-811K show that the accuracy rate of the I-CBAM-ResneXt50 can reach 96.96%. Compared with the existing algorithms, the proposed model can achieve better recognition and classification results. [ABSTRACT FROM AUTHOR]