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Abstract: Excellent ultra-shallow p+n junctions have been formed by thermally treating the BF2 +-implanted Si samples by excimer laser annealing (ELA) at 300–400mJcm−2 with post low-temperature long-time furnace annealing (FA) at 600°C. A junction with a leakage current density lower than 20nAcm−2 and a sheet resistance smaller than 200Ω□−1 can be well achieved. No considerable dopant diffusion is observed by using this low-thermal-budget annealing process. However, by simply using the ELA treatment at 300–400mJcm−2, the resultant junction shows a leakage current density as high as 104 nAcm−2 and a peripheral leakage current density of 103 nAcm−1. The large junction leakage is primarily due to the leakage current generated within the junction region near the local-oxidation-of-silicon (LOCOS) edge, and which is substantially caused by the ELA treatment. The large peripheral junction leakage current density can be significantly reduced to be about 0.2nAcm−1 after a post low-temperature FA treatment at 600°C. As a result, the scheme that employs ELA treatment with post low-temperature FA treatment would be efficient for forming excellent ultra-shallow p+n junctions at low thermal budget. [Copyright &y& Elsevier]

The instability mechanisms of passivated and non-passivated low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) under various bias stress conditions have been investigated. Irrespective of plasma treatment, the degradation was more severe under negative gate bias stress than that under positive gate bias stress. This could be due to Fowler–Nordheim tunneling electron induced impact ionization. For hot carrier stress, TFTs with NH3 plasma treatment degraded more severely than those without plasma treatment. This might be attributed to collapsing of weak Si–H bonds in NH3-plasma passivated devices. For the high current stress, it showed the opposite results against hot carrier stress. [Copyright &y& Elsevier]