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Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective alternative to conventional CMOS-based integrated circuits. Modular design methodology in QCA domain has not been widely investigated. In this paper, an efficient module with fault tolerance is proposed, which can be employed to fabricate three-input and five-input majority gates that are the fundamental primitives for designing circuits in QCA. With cells omission in the versatile module, various logic gates will be achieved, such as Nand-Nor-Inverter (NNI) gate and And-Or-Inverter (AOI) gate. Moreover, in order to seek out an efficient full adder, five various QCA full adders are designed and exhaustively compared in terms of area, complexity, latency, reliability and power dissipation and also compared with existing fault-tolerant full adders. Two simulation tools, QCADesigner and QCAPro, are utilized in the waveform simulations for verifying the correctness of proposed circuits and power consumption, respectively. The analysis results reveal that full adder V has significant improvements in contrast to its counterparts with above criteria. To test the practicability of full adder V, multi-bit adders will be designed in single-layer and compared with previous adders in terms of area, complexity and QCA cost, which proves the merits of our work. [ABSTRACT FROM AUTHOR]

This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of –243 dB. It also consumes an area of only 0.022 mm² resulting in the best performance-area trade-off system presented up-to-date. [ABSTRACT FROM PUBLISHER]

We report a gas ionizer based on arrays of microfabricated double-gated isolated vertically aligned carbon nanofibers (VA-CNFs) for application in low-power portable mass spectrometers. Field-emitted electrons from VA-CNFs are accelerated to high energy and subsequently collide with neutral gas molecules, leading to ionization/fragmentation of the molecules. Double-gated field-emitter arrays with isolated VA-CNF tips were fabricated using a photoresist planarization technique. Two types of devices were fabricated and characterized. The first type of device has the emitter tip in the same plane as the extraction gate, and the second type of device has the emitter tip 900 nm below the extraction gate. All devices were made using a process that results in gate and focus diameters of 1.7 and 4.2 \mu\m, respectively. When operated as a field-emitted electron impact ionizer (EII), for the same ion current, the ionization efficiency (ratio of ions to emitted electrons) increased from 0.005 to 0.05 as the pressure is increased between \5\times10^-6 and \1\times10^-3 torr. In comparison with EIIs based on thermionic electron sources, the power dissipation reduced from > 1 W to 100 mW. [ABSTRACT FROM AUTHOR]

Organization of functional checking of combinational circuits based on application of modified sum codes is studied. These codes refer to classes of codes with weighted digits and weighted carriers. Properties of codes and techniques for realization of check-out equipment are defined. [ABSTRACT FROM AUTHOR]

Reconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and develop a technology mapping tool. The key feature of the VGLC architecture is that the variable granularity is a tradeoff between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. Finally, we evaluate the proposed logic cell using the newly developed technology mapping tool, which improves logic depth by 31% and reduces the number of configuration data by 55% on average, as compared to the Virtex-4 logic cell architecture. [ABSTRACT FROM AUTHOR]

The particular behaviour of latch circuits caused by marginal triggering is analysed in this paper. Simple theoretical models including simulation circuits are suggested for the study of logical circuits based on any technology. The different waveforms observed in experiments at the latch or flip-flop output have been explained in theory. Apparent hesitation which can be responsible for coherence faults introduced by the synchronizers in random access synchronous systems is explained in detail. [ABSTRACT FROM AUTHOR]

Graphene is a new promising candidate for application in radio-frequency (RF) electronics due to its excellent electronic properties such as ultrahigh carrier mobility, large threshold current density, and high saturation velocity. Recently, much progress has been made in the graphene-based RF field-effect transistors (RF-FETs). Here we present for the first time the high-performance top-gated RF transistors using millimeter-scale single graphene domain on a SiO2/Si substrate through a conventional microfabrication process. A maximum cut-off frequency of 178 GHz and a peak maximum oscillation frequency of 35 GHz are achieved in the graphene-domain-based FET with a gate length of 50 nm and 150 nm, respectively. This work shows that the millimeter-scale single graphene domain has great potential applications in RF devices and circuits. [ABSTRACT FROM AUTHOR]

Highly efficient power-gating systems beyond conventional CMOS technology could be realised using a new non-volatile flip-flop design based on a 'pseudo-spin-MOSFET' (PSMOSFET), researchers in Japan have shown. The non-volatile flip-flop architecture is faster and uses less power than other backup architectures using ordinary flip-flops, and is compatible with existing CMOS fabrication and circuit technologies. [ABSTRACT FROM AUTHOR]