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With the advert invention of wireless fidelity commonly called as Wi-Fi in the field of communication and computer networks a new era or revolution has taken place. In the recent twenty years, numerous IEEE 802.11 technologies have been developed for Wireless Local Area Network (WLAN) connectivity. The common point of these technologies is that the latest IEEE 802.11 version has always several advanced features compared to its predecessor. Simultaneously, testing this technology standard parameter is a challenge in the ATE production environment. One of the key standard parameters in radio receiver specification is Packet Error Rate (PER) which is a direct measurement of field parameter. In this paper, a detailed implementation of WLAN Rx PER test in Production Automated Test Equipment (ATE) environment with parallel testing is described and studied. This study incorporates efficiency of implementation, yield improvement of 2% and test time comparison with respect to legacy test methodology.

In last decade, SiGe BiCMOS technologies open a new cost-efficient market first at mm-wave frequencies, then at sub-THz and THz range. Starting with the commercial use of automotive radars at 77 GHz, and the demand for 120/140 GHz radars, the market now has a strong interest on low-cost silicon based technologies for such high frequencies. The driving force behind the BiCMOS is not anymore only radar applications but also 5G/6G communication systems, operating at 60, 140 or even 240/300 GHz. Furthermore, the strong need on the driving circuitries of photonics components has created a mass market of high speed communication circuitries. The latest developments on SiGe HBTs with fmax of beyond 700 GHz boosts the research and development effort on circuit and system area to take share from the new markets. In parallel to the developments on SiGe HBT performance, “More-than- Moore” path, which covers all the additional functionalities to the standard CMOS process (i.e. MEMS devices, microfluidics, photonics, etc…), allows to realize multi-functional circuits and systems. Heterogeneous integration as a key and enabler technology for the multi-functional systems has also great importance these days. Hetero integration of different technologies such as high scaled CMOS, SiGe BiCMOS or even III-V ones has become real. Such integration of multi-chip technologies provides the highest performance with the most efficient size and power consumption; thus paves the way for next generation smart systems integration. In this talk, approaches used for the integration of different More-than-Moore modules into a BiCMOS process will be presented. New hetero-integration technologies and corresponding challenges will be discussed.

In this paper, we introduce a novel design for test (DFT) concept to check the compliance of wireless-body-areanetwork devices for medical applications with the spectral mask for IR-UWB and FM-UWB defined in chapter 9.13 of the IEEE Std. 802.15.6-2012. The design enables a fast and repeatable ICproduction test solution for medium to high volume testing, which is independent of the tester type and does not need any extra circuitry on a test board / device interface board.

This paper presents a powerful combination of Analog Mixed-Signal (AMS) verification in combination with emerging IEEE P1687.2 standard, capable of enabling automation of the large part of test pattern generation flow from the specification to Automatic Test Equipment (ATE). The inherent property of AMS verification to incorporate UVM based environment and a configuration with design modules described at arbitrary abstraction levels allows efficient pre-silicon test setup simulation. UVM also facilitates automated generation of STIL, used as the main vehicle to trigger various ATE instruments. The approach is piloted on a power amplifier product that contains BigA and notso- small D portion. To the best of our knowledge, this is the first proposed self-containing flow that achieves test development reduction and provides guidance for test quality improvement while relying entirely on emerging and existing IEEE standards.

The widespread usage of Long Short-Term Memory (LSTM) accelerators in time-series related applications necessitates using a protection mechanism against faults caused by wear-out and environmental effects. This paper proposes a Concurrent Error Detection (CED) scheme combining low overhead duplication and residue codes to detect faults in multiply and add stages of LSTM accelerators. For the multiply stage, the CED consists of a multiplier for every LSTM multiplier with a temporal selection of data. For the add stage, the CED adders are shared among the LSTM adders, thus spatial selection is performed. The experimental results show that the proposed method yields good detection probability with a lower area and power overhead in comparison with the traditional duplication techniques that indiscriminately duplicate all hardware structures all the time.

We propose TaintLock, a lightweight dynamic scan data authentication and encryption scheme that performs perpattern authentication and encryption using taint and signature bits embedded within the test pattern. To prevent IP theft, we pair TaintLock with truly random logic locking (TRLL) to ensure resilience against both Oracle-guided and Oracle-free attacks, including scan deobfuscation attacks. TaintLock uses a substitution-permutation (SP) network to cryptographically authenticate each test pattern using embedded taint and signature bits. It further uses cryptographically generated keys to encrypt scan data for unauthenticated users dynamically. We show that it offers a low overhead, non-intrusive secure scan solution without impacting test coverage or test time while preventing IP theft.

Aging degradation dominated by bias temperature instability (BTI) effect is one of the important considerations in system on chip (SOC) design margin. Research on path delay with BTI recovery effect which mitigates degradation is meaningful to set a reasonable aging margin. Since BTI recovery effect known in transistor level occurs very fast, it is a challenge to sample aged path delay in a short interval. In this paper, we propose an aging monitor to investigate the impact of BTI recovery effect on path delay degradation (Δdelay) in nanosecond intervals. The results show that the power function of recovery time accurately fits the trend of Δdelay after the removal of stress. The higher the stress voltage, the faster the absolute value of Δdelay recovers. Increasing stress time obviously reduces the recovery speed of Δdelay. It’s note that BTI recovery effect occurs not only after the removal of stress but also during AC stress. Therefore, the Δdelay is so dependent on stress type that the Δdelay with BTI recovery is 0.2 times of that without BTI recovery. The silicon data also contributes to aging model’s calibration by the introduction of BTI recovery coefficient, which has a ~4% design margin benefit in a 1GHz SOC design.

While the importance of parallel hardware architectures has been increasing over the decades, software tends to be one step behind. In the testing and reliability field, noncommercial software is often designed with few to no parallelism in mind. In this paper, we focus on a toolchain that allows us to measure the stress metrics of large SoC through the analysis of enormous Value Change Dump files produced by the testing and simulation equipment. In this toolchain, we concentrate on speeding up the analysis and making the entire process more automatic through pipeline and parallelization techniques. We tested the resulting Burn-In test application on a real chip, developed by STMicroelectronics.

Failure diagnosis is a software-based data-driven procedure. Collecting an excessive amount of fail data not only increases the overall test cost, but may also lead to degradation of diagnostic resolution. Test-termination prediction is thus proposed to dynamically determine which failing test pattern to terminate testing, producing an amount of test data that is sufficient for an accurate diagnosis analysis. In this work, we describe a novel data-model co-design method of using deep learning method for efficient test-termination prediction. In particular, images describing the failing test responses are constructed from failure-log files. A multi-layer convolutional neural network (CNN) embedding a residual block is then trained, based on the images and known diagnosis results. The learned CNN model is later deployed in a test flow to determine the optimal test-termination for an efficient and quality diagnosis. Experiments on actual failing chips and standard benchmarks demonstrate that the proposed method outperforms SOTA works. Our method creates opportunities to harness the power of deep learning for improving diagnostic efficiency and quality.

In-field test of integrated circuits using Self-Test Libraries (STLs) is a widely used technique specifically suited to guarantee the processor’s correct behavior during the operative lifetime, as mandated by functional safety standards such as ISO26262. Developing STLs for stuck-at faults requires significant manual efforts from test engineers, and targeting delay faults is even more challenging. In order to support this process, in this paper we propose a method to automate the creation of STLs targeting delay faults starting from existing STLs targeting stuck-at faults. The method is based first on identifying excited but not-observed transition delay faults and then adding suitable instructions able to detect them. Experimental results on a RISCV processor show that the method can systematically detect a significant percentage of the target faults with reasonable computational effort and test code size increase.

The IEEE Std 1687 (IJTAG) provides enhanced access to the on-chip test instruments, which are included on the chip for test, post-silicon debug, in field maintenance, and diagnosis purposes. Although the on-chip instruments access provides data and features explicitly for test and debug, these features are misused by the malicious user to access sensitive data such as encryption keys, Chip-IDs, etc. Hence, it is desired to limit the access to sensitive on-chip instruments via IJTAG network. One of the various schemes proposed to mitigate the vulnerability of the IJTAG network is to use a secure access protocol, which is based on LSIB, Chip-ID, and licensed access software. In this paper, the detailed security analysis is performed on IJTAG, it is shown that the secure access protocol technique is vulnerable to differential analysis attack. It can be used to break the secure communication between the board and the licensed access software and thus, the sensitive on-chip test instruments can be accessed illegitimately. It is shown that our proposed algorithm can recover the template used for secure communication within a fraction of a second.

Multi-tenant FPGAs are increasingly being used in cloud computing technologies. Users are able to access the FPGA fabric remotely to implement custom accelerators in the cloud. However, sharing FPGA resources by untrusted third-parties can lead to serious security threats. Attackers can configure a portion of the FPGA with a malicious bitstream. Such malicious use of the FPGA fabric may lead to severe voltage fluctuations and eventually crash the FPGA. Attackers can also use side-channel and fault attacks to extract secret information (e.g., secret key of an AES encryption module). We propose a convolutional neural network (CNN)-based defense mechanism to detect malicious circuits that are configured on an FPGA by learning features from the data-series representation of the bitstreams of malicious circuits. We use the classification accuracy, true-positive rate, and false-positive rate metrics to quantify the effectiveness of CNNbased classification of malicious bitstreams. Experimental results on Xilinx FPGAs demonstrate the effectiveness of the proposed method.

Power handling during test is an important requirement that needs to be considered during chip design, silicon bring-up, and in-system testing. In this tutorial, we will start by reviewing the importance of power and listing the different problems faced with poor power intent. We will then give an overview of different power aspects related to test, from RTL implementation to in-system validation, and how each step can impact the overall performance. Next, we will introduce different design-for-test (DFT) techniques that help improve power planning to produce optimized quality of results (QoR). Finally, we will present data sets on how each of the listed techniques implemented on real designs produces desired results.

Stochastic computing (SC) with its stream-based, probabilistic number representation promises large area and power benefits as well as increased error tolerance compared to conventional binary computing. While SC is less precise, it is considered a promising option for implementing neural network inferencing in ultra-low-power edge devices. SC-based Neural Networks (SCNNs) typically combine stochastic and binary components for interfacing and to alleviate certain SC limitations. Moreover, ultra-low-power VLSI for edge computing is often less reliable due to noisy environments or deliberate power-reliability trade-offs. In this work, we present the first detailed investigation of the behavior of an SCNN and its individual components on hardware prone to timing errors. Our results show that robustness of SC is highly dependent on specific design choices and that biases in the error distributions may even cause SCNNs to perform worse under certain circumstances than comparable binary implementations. It shows that robustness should be treated as a design goal in SC rather than taken for granted.

In-system deterministic tests are used in safetysensitive designs to assure high test coverage, short test time, and low data volume, typically through an input-streaming-only approach that allows a quick test delivery. The output side of the same scheme is, however, inherently vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to the last-minute timing violations. Typically, X values degrade test results and thus test response compaction requires some form of protection. This paper presents two X-masking schemes that complement the primary (or level-A) blocking of unknown values by filtering out those X states that escape the first stage of masking and shall not reach a test response compactor or test result sticky-bits deployed by the on-chip compare framework. Experimental results obtained for eleven industrial designs show feasibility and efficiency of the proposed schemes altogether with actual impact of X-masking on various test-related statistics.

Boosting hardware design productivity is a major plus of SpinalHDL, a Scala-based Hardware Description Language (HDL). SpinalHDL achieves this by providing object oriented programming, functional programming, and metahardware description finally enabling the generation of Verilog code. Despite all the advantages of SpinalHDL, verification is the biggest challenge here as well. In this paper, we bring Coverage-Guided Fuzzing (CGF), a wellestablished software testing technique, to the SpinalHDL design flow. We have implemented our approach SPINALFUZZ on top of the fuzzer AFL++. We leverage Scala-features to automate as many tasks as possible and ease the integration of fuzzing in SpinalHDL. In the experiments we demonstrate the effectiveness of SPINALFUZZ in comparison to Constrained Random Verification (CRV). For a wide range of SpinalHDL designs we show that SPINALFUZZ outperforms CRV and reaches coverage-closure.

In this work, a comparative study between established Control Flow Checking (CFC) techniques is presented. A novel test bench is used to inject permanent falts into an emulated microcontroller. This test bench manages all the assessment phases, from fault generation to fault injection to results classification. Results are presented comparing the attained results in terms of the ability to detect permanent faults.

The work presented here is on back-annotation of physical properties into components of an embedded system for system-level simulation and facilitating fast design space exploration. Two important properties, power and noise are considered in this thesis. A general ML-based framework is proposed for both power and noise back-annotation. This framework removes the expensive low-level simulations and performs a one-time offline effort for low-level property characterization. The actual data from characterization generates the dataset for training ML-based models. We evaluate several ML techniques on this task like multi-layer perceptron, convolutional neural network, gradient boosting, and LSTM. The trained model will be implemented in a fast SystemC surrogate model that speeds up the simulation time for system design space exploration. In this paper the methodology will be explained for interconnect crosstalk back-annotation. A crosstalk model for a RISC-V like processor interconnects is implemented and evaluated as a case study. The same methodology is used for backannotating and evaluating processor power at system level.

The ever-increasing demands of high-performance visual and accelerated computing has resulted in GPUs becoming some of the most complex ASICs being built today. The last few years have also seen an explosion in demand for unique silicon designs serving varied markets such as gaming, HPC, healthcare, smart cities, robotics and automotive. Process scaling is an important factor of delivering such continuous performance gains over the decades. Some of these designs push the limits of current chip manufacturing technology, growing to 80B transistors and beyond. Furthermore, these new designs are implemented with innovative new methods in physical design and are accelerated to reach the market at a staggering pace. Delivering outgoing quality in such an expeditious development environment presents unique test challenges related to test time, cost, power, advanced defectivity and diagnosability to list a few. Current industry practice for structural testing of SOCs requires expensive automatic test equipment (ATE). As chip sizes grow exponentially, demand for memory per IO increases to meet low DPPM (defective-parts-permillion) requirements. In most cases, neither additional IOs are available for test, nor the speed of test paths through the IOs improve. With 2.5D and 3D chips becoming more mainstream, IOs available for test have further decreased. Scan compression schemes come at the cost of poor diagnosability or vendor specific design customizations thereby increasing the chip costs. This causes the test cost to increase drastically. As chip volumes grows and 3D integration gets more adoption, it is critical to catch defects as early in the test flow as possible given the cost of waste that otherwise would accumulate. This makes ATE to system-level test (SLT) correlation one of the key factors, which has been historically a major challenge for test. In the small fraction of cases where it is possible, the cost of running structural tests on SLT environment is very expensive, which makes this process impractical. Universal EDA solutions for bridging the ATE-SLT correlation gap do not exist or are not practical. As a new application to DFX design space, automotive and high-performance computing (HPC) markets require periodic in-field testing for safety and reliability. Structural tests provide extremely high coverage compared to functional patterns and most suited to satisfy the requirements of these segments. Existing schemes for in-field structural testing are limited due to long run times and/or low coverage. Additionally, the application of the structural patterns needs to be extremely secure to protect the confidential assets, which makes it even harder. With the advent of sub-5nm transistor technologies, standard solutions that only look at tests’ pass/fail results are not sufficient to catch marginal defects that are hard to detect. In the era of machine learning, we need look beyond test results and what human experts can see, into anomalous chip parameters in a sea of complex data. DFX design space is expanding and rapidly changing, and it is not yet fully serviced by existing EDA solutions. Hence, current requirements push us to innovate across the spectrum of DFX architectures. This talk will provide a summary of various ideas used at NVIDIA to tackle these challenges: Using functional high-speed interfaces for test-data transfer, portable test solutions, programmable test architectures, improved design-for-debug features, emulation for DFX, and using machine learning to solve DFX problems.

It is well known that during device testing, the switching activity (SWA) of the circuit under test (CUT) is an important parameter that must be retained to a minimal value in order to avoid unwanted scenarios on the CUTs (e.g., over-stressing) that can lead to an artificial yield loss. However, there are scenarios, e.g., during Burn-In testing (BI), where the maximization of the SWA can be proven beneficial by accelerating the aging phenomena of the devices in a safer and better controlled manner. In the frame of my PhD activities, I look for new methods able to automatically generate programs able to maximize the switching activity in a SoC and/or in the single modules within it. I already developed two methods while considering microprocessors as case studies, that automate the generation of stress-inducing stimuli for various units of a pipelined CPU. The first method is based on evolutionary techniques, while the second is based on formal techniques. The microprocessor we considered is the OpenRISC 1200 (OR1200).

Improving Test Quality and Reliability via In-system/In-field Testing Lee HARRISON (Siemens EDA – United Kingdom) How ACS enables an Open Innovation Ecosystem for AI/ML applications in the Semiconductor Value Chain Matthias SAUER, Sonny BANWARI (ADVANTEST – Germany) The Need for New DFT Approaches to Scan Thomas KOEHLER (TERADYNE, Germany)

Strategies for Enabling Quantum Development with Test and Measurement at millikelvin range focusing on pre-characterization. Jack DEGRAVE1, Philip KRANTZ2, Dong-Thuc KNOBBE1 1FormFactor, USA, 2Keysight, USA Challenges and Solutions for Automotive Cold Test Elimination. Chen HE NXP Semiconductors, USA RETE: DfRT, Test for Reliability & Data Analysis for zero defects and zero scraps. Mauro PIPPONZI, Alessandro MASERI, Luca MORICONI ELES Semiconductor Equipment, Italy 3D interconnect Test Challenge. Sreejit CHAKRAVARTY Intel, USA

IEEE 1687-2014 gained traction in the test community very fast. Numerous innovations, publications, and implementations have been described, from both, industry and academia. Today, 7 years plus a few months after the release of the standard, much of the commercial test infrastructure is based on IJTAG. It is supported by all three major EDA tool vendors. In addition, derivatives of IEEE 1687, namely IEEE P1687.1 and P1687.2 are in active development. This is not to say that the original IEEE 1687 standard is without flaws. The 1687 working groups has actively collected not only errata, but also requests from users and tool developers alike, asking for upgrades to the standard, if it ever will be reopened. This time has finally come. In January 2022, Jeff Rearick had submitted a modified PAR, initiating the process. This PAR was subsequently approved, and with that, the P1687 is now officially open for upgrades.

The technology evolution has tried to address the demand for faster computers. Despite the achieved speed-up in terms of memory and computation performances, the communication between the memories and the processor remains a bottleneck. The Computation in-Memory (CIM) aims to solve this problem by moving the computation directly inside the memory. This study focuses on the Logic-In-Memory (LIM), which represents the applications that accelerate Boolean Logic. This paper introduces the analysis of selected Logic-In-Memory operations simulated under various operating conditions. This is the preliminary step to study the behavior of LIM for security applications.

High-quality memory diagnosis methodologies are critical enablers for scaled memory devices as they reduce time to market and provide valuable information regarding test escapes and customer returns. This paper presents an efficient Hierarchical Memory Diagnosis (HMD) approach that accurately diagnoses faults in the entire memory. Faults are diagnosed hierarchically; first, their location, then their nature (i.e., static or dynamic), and finally, their functional fault model. The HMD approach leads to a more accurate diagnostic, enabling the precise identification of yield loss causes.

With deep submicron scaling, soft error has become one of the major reliability challenges for electronic systems. This work proposes a Machine Learning-based Checker (MLC) to protect hard-core processors against radiation-induced soft errors. MLC is an independent hardware unit that implements an ML algorithm to detect soft errors in a processor and works in a parallel fashion with that. This work considers XGBoost as a lightweight and high-performance machine learning method. XGBoost is trained based on some programmers’ view features of the processor like control signals. The proposed scheme is applied to a RISC-V-like processor, called SAYAC, as a case study.

Crosstalk noise has been strongly threatened the signal integrity of interconnects in new sub-micrometer technology nodes. The crosstalk prediction helps to avoid crosstalk consequences. Static crosstalk models cannot predict crosstalk faults intensified by thermal, fab-induced, and temporal uncertainties. The goal of the paper is to avoid crosstalk by the use of a dynamic crosstalk predictor which can adapt itself in the presence of uncertainties. To begin with, the neural network model of the crosstalk phenomenon would be extracted based on data transition of communication wires. This model is implemented as an on-chip crosstalk predictor. In addition, this predictor would be trained on-chip by hardware implementing the learning algorithm. Simulation results show that the proposed predictor is much more tolerant of uncertainties than the static predictors.

The complexity of automotive Systems-on-a-Chip (SoCs) has enormously grown in the last decades. Today’s automotive SoCs are compelling due to technology improvements, different integration technologies, increased heterogeneity, and many available embedded memories. On balance, despite testing techniques that have been refined through years, traditional structural test methods, like scan and BIST, can cover a vast but not complete spectrum of all the possible defects. It appears that the divide-and-conquer approach founded on structural techniques may not be enough to reach every single element or to effectively stimulate the faulty behaviors that may show up during the lifetime of the device. Burn-In is widely used to reduce Infant Mortality, accelerating the evolution of weak points into defects via externally or internally induced stress. In this work, we focus on internal stress and present a generation strategy intended to automatically produce functional stress procedures for the Burn-In phase that exacerbate possible weak points which are likely to escape activation by structural tests, such that they more easily outbreak during the successive final test procedures. The proposed generation strategy primarily addresses the interconnections to embedded memories, which look challenging to stress by structural methods, including Logic and Memory BIST, and critical due to the integration of different technologies (i.e., logic gates and memory layout). In the considered test case, the proposed approach increases the average toggle activity by orders of magnitude with respect to Memory BIST. Furthermore, it provides a uniform distributed toggling activity. Results collected on an automotive SoC show how the stress provided by functional programs compares with the stress level provided by structural test methods measured in terms of toggling activity. The SpeedUp produced by the proposed procedure is 3.14X wrt to the MBIST executing the March C-algorithm.

Memory requirements are constantly increasing in System on Chip (SoC) devices. To keep on with this demand, manufacturers rely on embedded Flash memories that are easily scalable and relatively cheap to manufacture. These memories usually take a large percentage of the die area, and their reliability and verification process are thus two of the critical factors for a high yield. The testing efforts ensure that each commercialized device is compliant with the provided specifications but has to deal with a set of faults specific to embedded flash memories. Tests must span from pure analogic power measurements to individual cell-by-cell functionality checks. For the latter, Built In Self Test (BIST) is the most efficient solution given its orders of magnitude reduction in test time (compared to CPU-controlled tests), with a minimal cost due to the increased circuit complexity and die area. Given the regular structure of flash memories, BISTs are easily implemented and replicated multiple times. Such testing solutions allow the verification of all the banks in parallel, further increasing the advantages of the BIST. Carefully organizing both hardware and software components of the BISTs may lead to a significant reduction in test time without affecting the final test quality. Looking at it from another perspective, the BISTs may generate a considerable amount of diagnostic data during the tests. Efficiently collecting this data is crucial for designers and test engineers who can improve the production process or strengthen their design. An intelligent solution for this task is an on-chip method to compact diagnostic information during embedded memory testing. This strategy permits the reconstruction of failure bitmaps without any loss. The proposed method uses a fraction of the memory requested by a coordinatebased bit mapping approach. At the cost of a moderate test time overhead, this strategy permits dramatically increasing the number of devices that can be fully diagnosed without any bitmap reconstruction loss.

Currently, Deep learning and especially Convolutional Neural Networks (CNNs) have become a fundamental computational approach applied in a wide range of domains, including some safety-critical applications (e.g., automotive, robotics, and healthcare equipment). Therefore, the reliability evaluation of those computational systems is mandatory. The reliability evaluation of CNNs is performed by fault injection campaigns at different levels of abstraction, from the application level down to the hardware level. Many works have focused their effort on evaluating the reliability of neural networks in the presence of transient faults. However, the effects of permanent faults have been investigated at the application level, only, e.g., targeting the parameters of the network. This paper presents the ongoing work on the reliability evaluation of CNNs targeting permanent faults in GPU devices, considering different fault injections levels. Our preliminary results show that the fault injections performed at the application level generate more optimistic results than considering an architectural level fault injection.

As any other circuits, secure devices need to be tested to ensure their reliability. Nevertheless, test infrastructures, such as JTAG or scan chains, can maliciously be used to steal secret data stored or processed in secure devices. In this paper, we explore a lightweight solution to protect JTAG access based on a challenge-response authentication protocol. A JTAGauthentication dedicated IP is presented. Design alternatives for quick IP plug-and-play, security, area and test time optimization are presented and evaluated.

Embedded memories in Automotive Systems-on-Chip usually occupy a large die area portion. Consequently, their defectivity can strongly impact production yield for any automotive device. Along with the technology ramp-up phase and for statistical process control reasons during volume production, it is a good automotive industry practice to collect diagnostic information in addition to pure testing data. Designers and technology experts must receive accurate diagnostic results from failing devices to react to misbehavior by identifying and correcting the related issues at their source and drawing correct repair strategy conclusions. A commonly used approach resorts to the generation of failure bitmaps based on collecting all failing bits coordinates to be sent one by one to the tester. More efficiently, the encountered faults can be compacted or compressed in onchip memory resources to be retrieved by the tester at the end of the memory test. This paper presents an on-chip method to compact diagnostic information during embedded memory testing. More specifically, the method is applied to diagnose embedded FLASH memories. This strategy permits the reconstruction of failure bitmaps without any loss, while compression approaches obtain an approximation. The proposed method uses a fraction of the memory requested by a coordinate-based bit mapping approach and is comparable to compression methods. At the cost of a moderate test time overhead, the proposed strategy permits dramatically increasing the number of devices that can be fully diagnosed without any bitmap reconstruction loss. Most failing devices in a real embedded FLASH production scenario were diagnosed after a single transfer from on-chip to the tester host computer.

In this paper we propose an on-line test methodology for RO-PUF reliability which enables high accuracy in the results since it is not based on predictive simplified models of the device variability and noise, but on actual technological electrical models and high versatility since it is not based on measurements extracted from a single technology.

Root Cause Analysis (RCA) and Layout Pattern Analysis (LPA) are critical technologies for Diagnosis Driven Yield Learning in designing and manufacturing integrated circuits. Recent advancements of AI technologies can help improving yield learning accuracy and transferring the yield learning experiences from old designs to new designs or from old technologies to the new ones. In this talk, we share our experiences in this research area and discuss the following techniques: (1) A neural-network-based framework for RCA. The framework has a self-adaptive module that is able to adapt the inference module to new designs and new technologies based on a few new samples. (2) An encoder network framework for LPA. It applies Contrastive Learning to extract representations of layout snippets that are invariant to trivial transformations such as shift, rotation, and mirroring. The layout snippets are then clustered to form layout patterns. The causal relationship between any potential layout patterns and the systematic defects is identified by the Causal Representation Learning. (3) An unsupervised learning framework by using a Deep Latent Variable model consisting of a probabilistic encoder and a regularization decoder. The encoder transforms the features from diagnosis reports to latent variables characterizing the root cause distribution. The regularization decoder uses a Graph Attention Network to represent the mapping from the true root causes to suspicious root causes reported.

Computation-In Memory (CIM) using RRAM crossbar array is a promising solution to realize energy-efficient neuromorphic hardware, such as Binary Neural Networks (BNNs). However, RRAM faults restrict the applicability of CIM for BNN implementation. To address this issue, we propose a fault tolerance framework to mitigate the impact of RRAM faults on the accuracy of CIM-based BNN hardware. Evaluation results using MNIST, Fashion-MNIST and CIFAR-10 datasets demonstrate that the proposed framework outperforms the related works as it restores more than 99% of the RRAM fault induced accuracy reduction with relatively less overhead.

This paper describes a low-cost technique for extracting parameters of interest for test boards used in multisite automatic test equipment (ATE). In the proposed approach, physical elements and nets on the PCB are represented as a graph with nodes and edges. Graph traversal algorithms are then used to extract data about the connections between specific components on each test site. This approach automates the previously slow and manual process of generating the topology files necessary to extract board parameters. The proposed method is implemented on a multisite test board, and results are presented.

In this paper, we propose a TC clustering method that simultaneously considers two data groups: the I/O workload and the function coverage for a higher level of firmware testing. Subsequently, we introduce an application model that predicts the function coverage using only the I/O workload of the TCs from the above method.

The time required for testing silicon defects continues to rise as design complexity and transistor count increases in-line with Moore’s Law. Structured test, particularly scan compression, assists with reducing the amount of time and effort involved. Furthermore, the associated design-for-test (DFT) is often reusable for determining the root cause of defective silicon behavior. However, new challenges associated with higher system integration, such as 3D-IC and chiplet packaging technologies, and shrinking time-to-market, requires a new approach to achieve low defect levels and gain understanding of defective or abnormal behavior This relatively new approach is known as Silicon Lifecycle Management (SLM) and enables testing and analysis throughout the different silicon life phases, and utilized analytics (diagnostics) to improve each phase from design to in-field operation. This presentation covers a discussion on SLM that is built on in-chip environmental, structural, and functional monitors and can leverage DFT hardware to enable deep insights from silicon die to assembled systems. We discuss the similarities to a structured manufacturing test flow such as implementation, data acquisition from the silicon, analytics on the data, and corresponding corrective action. Additionally, key differences are pointed out, especially regarding real-time or in-situ operational requirements. Data is gathered at every opportunity during the device lifecycle providing continuous analysis and actionable feedback. With respect to test methods such as stored manufacturing test patterns or built-in-self test, SLM extends the ability to test beyond die and package phases, enabling testing silicon throughout its life cycle.

Studying the radiation effects on electronic devices is essential for avionics and space systems. The shrinking technology nodes and increasing density of devices enhance the sensitivity of electronic systems to ionizing radiation. Due to their crucial role, memories and processors are the highest contributors to soft errors in systems, making them the best candidates for studying these effects. This work introduces the radiation environment in space and atmosphere and the main effects that the different types of ionizing particles that are present in these environments may produce on electronic devices. Furthermore, mainly focusing on Single-Event Effects (SEEs), it presents approaches and tools for modeling SEEs and their impact on memories and microprocessors. Additionally, experimental results targeting a Commercial-Off-The-Shelf self-refresh Dynamic RAM are presented. These experiments are based on radiation test campaigns in particle accelerators with neutrons and protons. Finally, an overview of issues and mitigation techniques for microprocessors is exposed.

Evaluating Burn-In related Metrics for large Automotive Systems-on-Chip. Francesco ANGIONE1, Paolo BERNARDI1, Andrea CALABRESE1, Stefano QUER1, Davide APELLO2, Vincenzo TANCORRE2, Roberto UGIOLI2 1Politecnico di Torino, Italy, 2STMicroelectronics, Italy MBSA Approaches Applied to Next Decade Digital Components. Tiziano FIORUCCI1, Jean-Marc DAVEAU1, Emmanuel ARBARETIER2, GIORGIO DI NATALE3, Thomas JACQUET2 1STMicroelectronics, Crolles, Frances, 2APSYS-AIRBUS, France, 3Univ. Grenoble Alpes/CNRS/TIMA, France Monitoring and controlling handler temperature. Guy DECABOOTER Onsemi, Belgium

Neural Networks (NN) can be efficiently accelerated using emerging resistive non-volatile memories (eNVM), such as Spin Transfer Torque Magnetic RAM(STT-MRAM). However, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed state and in turn, degradation of inference accuracy. We propose a design-time reference current generation method to improve the robustness of the implemented NN under different thermal and process variation scenarios with no additional runtime hardware overhead compared to existing solutions.