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This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking $\mu {\rm P}$ and high density cache memory, with $> 2~{\rm GHz}$ operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50 $\mu{\rm m}$ pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1 $\mu{\rm m}$ . The paper concludes with comments on the challenges for future 3D DRAMs.

High performance processors and ASICs typically require multiple voltages and multi-domain voltage controls across the die. Conventional approaches distribute the voltage regulation elements between the processor, the package laminate, and the printed circuit board. We propose an alternative approach where the voltage regulator is embodied in a 3D configuration such that the inductor, capacitor and the switches are formed on a separate silicon chip sandwiched between the processor and the laminate. Due to the close proximity of regulator to the processor, this approach can enable granular voltage domains, while minimizing disruptions to the processor layout. We describe a 4-f DC-DC buck converter fabricated on 32nm SOI wafers using TSVs to connect the switches on the front-side of the wafer to the inductors on the grind-side. The process builds on a 32nm SOI CMOS flow, adding deep trench (DT) capacitors and TSV's. Down conversion from a standard I/O voltage under various load conditions was evaluated, and an efficiency of 77% was achieved.

This study explores the reliability of a wireless sensing unit by testing it in a real-world university laboratory environment. The unit employs off-the-shelf products for their key components, while a flexible payload scheme was adopted for radio packet transmission to maximize throughput and minimize latency. The testing consists of two main parts: (1) a series of loopback tests using two off-the-shelf radio components with carrier frequencies of 900 MHz and 2.4 GHz, respectively, and (2) wireless transmission of a shake table response to a periodic swept sine excitation. The performance of the wireless channel is examined in each part of the study. Through this experimental investigation, it is validated that a loopback test may be used as a fast prototyping approach to characterize the complex transmitting environment of a structure in which a wireless monitoring system is installed. Various factors leading to signal attenuation are ranked according to their effects on packet delivery performance. Transmitting range and building materials are among the leading factors causing packet loss (and therefore data loss) in this specific testing environment. The severity of interference from 802.11b wireless systems in close proximity to the wireless sensing unit was investigated. Some preliminary results on the influence of operating rotating machinery and human activities are to wireless sensors were investigated. The results presented herein offer a guideline for applying wireless sensing within real-world structures so that the reliability of the wireless monitoring system is maximized. Due to uncertainties associated with the reliability of wireless communications, statistical analysis is performed on the collected time histories to reveal the underlying patterns associated with data loss. Temporal correlations of data loss were measured and found to be related to the adopted radio. A statistical distribution of the size of consecutive lost data points was further derived from the collected data. Such results have identified the need to further develop: (1) reliable communication protocols to reduce these losses in data and information, and (2) robust data processing and system identification tools to anticipate and explicitly handle any data loss. Copyright © 2007 John Wiley & Sons, Ltd.

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structural health monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.

To continue with the development of a wireless sensing unit built upon an off-the-shelf FPGA development board presented by the authors at SPIE 2005, this paper outlines a further effort consisting of embedding onboard computations, simulation and validation of the FPGA-based wireless sensing unit that is able to collect, process and transmit data. This research supports the concepts of decentralized wireless sensor networks and local-based damage detection, where individual wireless sensor nodes are capable of performing intricate tasks and can eventually transmit the processed results. An FPGA-based hardware platform is thus looked upon as a major contender for performing this function in a proficient manner. Throughout this research, the principal design complexities, in terms of both hardware and software development, are kept to a minimum. Development cycle and monetary cost of the hardware are other major considerations for this research. Data processing functions including windowing, Fast Fourier Transform (FFT), peak detection, are implemented into the selected FPGA, when limitations of different design options are explored to yield a solution that optimizes the resources of the selected FPGA. Numerical simulations and laboratory validations are carried out to scrutinize the operations and flexibility of the design.

This paper presents the preliminary results of an investigation on the application of Field Programmable Gate Arrays (FPGAs) to civil infrastructure health monitoring. An off-the-shelf FPGA development board available at a comparable price to microprocessor development boards is adopted in this study. Advantages, disadvantages, feasibility and design concerns when using such a reconfigurable hardware architecture for implementing algorithms for structural health monitoring in a wireless sensor unit are studied in a showcase of implementing Fast Fourier Transform (FFT) in a wireless data transmitting setting.

This paper presents the preliminary findings of a study on data and system identification results (derived from collected data) in a wireless sensing environment. The goal of this study is to understand how various hardware design choices and operational conditions affect the quality of the data and accuracy of the identified results; the focus of this paper is packet and data loss. A series of experimental investigations are carried out using a laboratory shaking table instrumented with off-the-shelf Micro-Electro-Mechanical Systems (MEMS) accelerometers. A wireless sensing unit is developed to interface with these wired analog accelerometers to enable wireless data transmission. To reduce the overall design variance and aid convenient application in civil infrastructure health monitoring, this wireless unit is built with off-the-shelf microcontroller and radio development boards. The anti-aliasing filter and analog-to-digital convectors (ADC) are the only customized components in the hardware. By varying critical hardware configurations, including using analog accelerometers of different commercial brands, taking various designs for the anti-aliasing filter, and adopting ADCs with different resolutions, shaking table tests are repeated, the collected data are processed, and the results are compared. Operational conditions such as sampling rate and wireless data transmitting range are also altered separately in the repeated testing. In all of the cases tested, data is also collected using a wire-based data acquisition system to serve as a performance baseline for evaluation of the wireless data transmission performance. Based on this study, the challenges in the hardware design of wireless sensing units and data processing are identified.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.