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A single-chip IEEE-802.11g-compliant wireless LAN system-on-a-chip (SoC) that implements all RF, analog, digital PHY and MAC functions has been integrated in a 0.18-/spl mu/m CMOS technology. The IC transmits 0-dBm EVM-compliant output power for a 64-QAM OFDM signal. The overall receiver sensitivities are better than -92 and -73 dBm for data rates of 6 and 54Mb/s, respectively.

The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3×3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive I/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.

This paper presents a Bluetooth v2.1 compliant SoC that integrates all functions of a Bluetooth radio. The transceiver comprises a two-point modulated fractional-N synthesizer, a polar transmitter, and a 500 kHz IF receiver with minimal analog filtering. The radio architecture is chosen to minimize overall die area as well as power consumption for both the basic and enhanced data rates. The SoC is implemented in a standard 0.13 mum digital CMOS technology with a die area of 9.2 mm2, of which only 3.0 mm2 is occupied by the analog and RF blocks. The basic-rate radio draws a total supply current of 29.7 mA in the receive mode and 29.4 mA in the transmit mode.

This paper introduces a fully integrated 2x2 two-stream MIMO radio SoC that integrates all of the functions of an 802.11n WLAN. The 0.13 mum CMOS radio SoC, which integrates two dual-band (2.4 GHz and 5 GHz) RF transceivers, analog baseband filters, data converters, digital physical layer, media access controller, and a PCI Express interface, provides a low-cost low-power small-form-factor WLAN solution. The MIMO radio comprises two identical dual-band transceivers that share a common frequency synthesizer capable of operating in both integer-N and fractional-N modes. In 2.4 GHz mode, the transceiver uses a direct-conversion architecture with a 3.2 GHz fractional-N frequency synthesizer. Direct conversion is used primarily because of its simplicity and the area reduction it offers by eliminating the need for an IF path. A 3.2 GHz synthesizer frequency is used to avoid VCO pulling. The 3.2 GHz synthesizer output fvco is divided by two and then mixed with the original 3.2 GHz fvco to generate a 4.8 GHz frequency. This 4.8 GHz signal at twice the RF frequency is distributed to both transceivers. Within each transceiver, the 4.8 GHz signal is divided by two to generate the 2.4 GHz in-phase and quadrature LO signals. In the 5 GHz mode, the transceiver uses a sliding-IF dual-conversion architecture, in which the RF and IF LO signals are centered at 2/3 fRF and 1/3 fRF, respectively. The frequency synthesizer, operating in integer-N mode, thus provides a 3.2 GHz RF LO signal that is buffered and distributed to both transceivers. Within each transceiver a resistively loaded divide-by-two circuit is used to generate the quadrature LO signals at 1/3 fRF. The channel center frequencies in the 5 GHz band allow integer-N operation of the synthesizer with a relatively high reference frequency, thus improving the phase noise.

An RF front-end for a WLAN SoC is implemented in 0.18mum CMOS. It integrates a +20dBm PA, a high-sensitivity LNA, and a T/R switch. The T/R switch incorporates an impedance-transformation network to provide a receive S11 of -15dB at 2.4GHz and a sensitivity of -73dBm for a 54Mb/s 802.11g signal. For 64QAM OFDM at 2.4GHz, the TX EVM is -25dB at an output power of +16dBm.

An 802.11 a/b/g wireless LAN SoC for low-power embedded applications is implemented in a 0.18mum CMOS technology. The IC integrates the RF transceiver, digital PHY and MAC, CPU and host interface. For 64QAM OFDM, the 5GHz/2.4GHz TX EVM is -27.4dB/-27.5dB at an output power of -5.2dBm/-3.5dBm. Overall 5GHz/2.4GHz RX sensitivity is -73dBm/-76dBm at 54Mb/s