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In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18μm CMOS-MEMS technology, the post-layout simulation results show that our circuit consumes 30μW and 49μW in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of die-temperature is 0∼100°C with 0.05°C resolution.

In this paper, the authors present a configurable and power efficient multiuser MIMO-OFDMA baseband processor for uplink mobile communications. To solve the carrier frequency offset (CFO) problem in multiuser transmission, an inter-carrier interference-based (ICI-cancellation-based) CFO estimator is implemented based on an iterative search criterion of minimum signal-to-interference-noise (SINR) ratio. Compared to the state-of-the-art methods, the proposed CFO estimator is more robust to transmission configurations (MIMO and multiuser) and CFO variations. Moreover, the authors propose an efficient architecture that saves 78% of the hardware complexity compared to the direct implemented architecture by employing Taylor series expansion for ICI/multiple-access interference (MAI) cancellation. Meanwhile, a 2-D linear channel estimator is also proposed to assist the CFO estimator and track the time-variant multipath channel. Two kinds of MIMO detector, vertical Bell Laboratory layered space-time (V-BLAST) and V-BLAST with maximum likelihood (V-ML), are adopted to minimize output latency and achieve the best ML bit-error-rate (BER) performance. An ASIC fabricated by 0.13 μm 1P8M CMOS technology is measured with 2.31 Mbps/mW power efficiency and less than 1.5 dB implementation loss. In addition, the whole transceiver is integrated and verified by a system-on-chip (SoC) platform to demonstrate its efficacy.

Passive acoustic monitoring is effective for examining the temporal variation of cetacean occurrences through continuous recording. However, the interpretation of behavior variability remains difficult. Cetacean tonal sounds are believed to play an important role in communication. Changes in tonal sound usage can be indicative of changes in cetacean behavior. In this study, we applied a generalized tonal sound detector on recordings from the marine cable hosted observatory (MACHO) off Northeastern Taiwan. The tonal sound detector is a modified local-max detector, which examines the prominence of tonality in 2 ms time intervals. Detections were confirmed based on the short-time transient characteristic of tonal sounds. The burst pulse, fundamental frequency, and harmonic were separated during post-processing. The detection results can be used to analyze the frequency distribution and modulation of the tonal sounds. Following individual contour extractions, the tonal sounds were classified to examine the repertoire composition through duration and frequency normalization. An evident nighttime occurrence was identified for both the burst pulse and tonal sound. The mode frequency of tonal sound did not show a significant difference, but the percentage of overlapping tonal sounds, Shannon entropy of frequency distribution, and repertoire complexity varied significantly among diurnal cycles. The current framework of quantification on tonal sound modulation and repertoire complexity provides intuitive parameters for the variability of cetacean behavior, which can be used to examine the temporal variations of cetacean habitat use. The precision in distinguishing different species and behaviors may be increased by comparing the repertoire established through automatic classification.

In this paper, an efficient advanced RISC machine (ARM)-based system-on-chip (SoC) testbed for a multi-input multi-output orthogonal frequency division multiple access (MIMO-OFDMA) uplink transceiver is presented. To mitigate carrier frequency offset (CFO) and multipath channel impairments, low complexity architecture of an inter-carrier interference (ICI)-cancellation-based CFO estimator and a 2D channel tracker are proposed in the receiver. The proposed transceiver is integrated into the SoC platform and verified by a video codec. Moreover, the proposed testbed provides a fast and configurable HW/SW co-verification prototyping for single-input single-output (SISO)/MIMO-OFDMA systems.

Recently, orthogonal frequency division multiple access (OFDMA) systems gain more and more attention because OFDMA systems provide higher data rate, better spectrum efficiency and more flexibility in managing channel bandwidth than other systems. This paper describes the implementation of a multi-input multi-output (MIMO)-OFDMA uplink baseband receiver for 802.16e standard in system-on-chip (SoC) platform. As SoC design methodology becomes commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design requirements in shrinking time-to-market windows. For solving this problem, design reuse emerged as a possible approach to boost design productivity, and intellectual property (IP)-based design methodology has begun since the 1990s. The development of rapid prototyping testbeds with the SoC design methodology has given communication systems engineers the ability to implement and test their designs on real hardware in concert with the simulation stages.